The industry’s first complete UVM SystemVerilog VIP library

This positions Mentor as the first company to supply ASIC and FPGA SoC designers with a complete UVM SystemVerilog VIP library that covers the breadth of their peripheral interface, bus protocol and memory device needs. Providing the complete library in one consistent industry-standard format reduces the time it takes for engineers to set up verification runs, so they can focus on verifying unique, high-value parts of their designs.

The new memory library supports a wide spectrum of memory model variations including leading-edge protocols such as the high-bandwidth, low-pin-count HyperBus interface for HyperRAM and HyperFlash memory devices. It also supports a full range of DRAM models including DDR4, Low Power DDR4, Hybrid Memory Cube, High Bandwidth Memory-2 and the new JESD229-2 Wide I/O-2 standard. Finally, it includes a full complement of flash memory models including SDIO 4.1, SDCard 4.2, eMMC 5.1, ONFI 4.0, UF and serial, toggle, NAND and NOR flash.

Jackson Huang, Vice President, Segment and Ecosystem Marketing, Cypress Semiconductor, commented: “We’re excited about Mentor Graphics’ release of its extensive memory verification IP model library, in particular its support for the new HyperBus interface. We developed the HyperBus interface to achieve our increasing product performance goals with faster response times, without sacrificing breadth of functionality.”

Verification IP helps engineers reduce the time spent building testbenches by providing re-usable building blocks for common interfaces, protocols and architectures. Mentor’s memory VIP model library includes memory configuration software that allows customers to instantly generate fast, timing-accurate, validated memory models based on vendor, protocol and part number. In addition, Mentor’s unique 'reconfigurable-on-the-fly' architecture helps them evaluate second sources without recompilation or even restarting simulations.

“The vast majority of ASIC and FPGA project teams have moved to standard UVM SystemVerilog verification methodology and until now have been unable to find a universal VIP library that supports bus protocols, peripheral interfaces and memory devices, all in native UVM. Judging from initial adoptions of our new memory VIP library, it’s easy to see why verification IP is one of the fastest growing sub-segments in the functional verification market, now exceeding $110m in annual spending, according to the Electronic Design Automation Consortium,” said Mark Olen,  Product Marketing Manager, Design Verification Technology Division, Mentor Graphics.

The Mentor VIP library provides engineers with standard UVM SystemVerilog components using a common architecture across all supported protocols. This allows rapid deployment of multiple protocols within a verification team. Test plans, compliance tests, test sequences and protocol coverage are all included as SV and XML source code, allowing simple re-use, extension and debug. The Mentor VIP components also include a comprehensive set of protocol checks, error injection and debug capabilities. The new memory models are qualified on all industry-standard simulators.

Mentor VIP is a core technology in the Mentor Enterprise Verification Platform which boosts productivity in SoC functional verification for both ASICs and FPGAs by combining advanced verification technologies in a comprehensive platform. The Mentor EVP combines Questa advanced verification solutions, the Veloce emulation platform and the Visualizer debug environment into a globally accessible, high-performance, datacentre resource. The Mentor EVP features global resource management that supports project teams around the world, maximising both user productivity and total verification return on investment.