Ten years and counting

Where once the world could be split into analogue and digital, mixed signal is becoming the norm and with that comes an increasing level of complexity which chip designers have to tackle. One company that knows the problem well is Cadence Design Systems and this theme dominated its recent annual CDN Live event in Munich. 

Now celebrating its tenth anniversary, CDN Live attracts designers across all the verticals to hear the latest developments from the company. And it was this change to mixed signal that set the tone in Senior Vice President, Anirudh Devgan’s, opening keynote speech.
“Ten years ago, when CDN Live started, it was predominantly analogue and digital problems that we were solving,” he said. “Now it is mixed signal. The majority of our revenue is coming from 28nm designs, but the complexity is increasing no matter what process point you are at.”
He said the company was now adopting a three-prong strategy – system integration, package on board and the core chip-level electronic design automation (EDA), which was still the main part of the company’s activities.
“We are currently driving this three-level approach with our products,” said Devgan. “We are also looking at verticals such as automotive and mobile. Some of these have specific requirements, such as automotive, which has key safety requirements.”
Over the past two years, the company has introduced ten new products and Devgan said that came from the company being very profitable, which meant it was also very sustainable. “That has helped our R&D investment,” he said. “We are reinvesting in R&D. A lot of the ten new products were organically developed. We are an acquiring company but we have to make sure we develop products ourselves.”
He admitted that in the past the usability of Cadence products was somewhat lacking, and that the R&D team had been tackling this by integrating more blocks into the core products. “Now the user experience is a lot more pleasant,” he said. “We have integrated signoff. Customers can also now do very large blocks if they want. Timing is also a good example. We want to make sure you can seamlessly time between the pure digital and the analogue. We also want a common user interface across all the products.”
One company that has benefitted from this is ARM, most recently for the development of the Cortex A72, the company’s most advanced and highest performance processor, launched earlier this year. “We have been working very, very closely with ARM,” said Devgan. “Most of ARM’s internal development is done using Cadence tools, and that is a big change from three to four years ago.”
A major part of this was the Cadence Innovus implementation system that was formally announced in March and will have general availability from May. This has been out with some developers for the past six months and ARM used it during the development of the A72.

Debugging
The next step in product launches is Indago, formally announced at CDN Live. This is a debug platform that forms part of the company’s system development suite and is claimed to improve debugging productivity by up to 50 per cent. This is mostly due the company’s patented root-cause analysis technology that filters unneeded data not only to root out a single bug but to resolve the causes of related bugs.
Adam Sherer, Cadence’s Group Director for Product Management, said the concept of root-cause analysis was nothing new. “This is something that engineers have been doing since we invented the wheel,” he said. “But we have automated it.” This is part of a general problem that Cadence has observed.
“Software can be 80 per cent of the budget,” said Michael Siwinski, Vice President of Product Management. “But traditionally only 20 per cent of EDA is spent on automating software. There is a lot more that can be done on this, and we will continue to invest.”
The Indago platform uses a big data concept for hardware verification for intelligent debugging and increased automation. It is also scalable from IP to SoC level. Debugging, said Sherer, took up about half of an engineer’s time in the verification process. “Most of this is done by brute force,” he said, and could involve tens to hundreds of cycles making educated guesses regarding where to sample data and rerunning verification for each observed error. And increased SoC complexity is making this even harder.
“The key to solving this is root-cause analysis,” said Siwinski. “That is, trying to get to the root of the problem much more quickly.” The platform contains three task-specific debug apps: the debug analyser enables multi-language testbench debug; embedded software debug synchronises software and hardware source code debugging; and protocol debug allows the visualisation of protocol traffic and events captured by Cadence’s Verification IP platform. Another nine will be added later this year. “This is a new way to debug,” said Sherer. “This is not the way engineers operate today. It is a new concept.”

Fusion
The company was also celebrating the second anniversary of its acquisition of Tensilica, and to mark that was the launch of the Fusion digital signal processor based on the Xtensa customisable processor. The scalable DSP is suitable for applications requiring merged controller plus DSP computation, low energy and a small footprint. It is trying to capitalise on the growing Internet of Things (IoT) market by targeting SoCs for wearable activity monitoring, indoor navigation, context-aware sensor fusion, secure local wireless connectivity, face trigger, voice trigger and voice recognition.
“In the Internet of Things, the Fusion DSP is particularly targeted at the Things,” said Gerard Andrews, Senior Product Manager. “The three main functions of the IoT are sensing, computation and connectivity.”
The company is proud of its ability to allow the recognition of specific noises, such as a voice, in an otherwise noisy environment.
“A huge class of wearables will be voice controlled,” said Andrews, “and you need to do that efficiently. There will be no mouse, no keyboard, no large touchscreen. For a DSP, turning something on is easy but often turning it off is harder because of the noise of what has been turned on.”
This could be machinery in a factory or even a television in the home. This DSP combines flexible hardware choices with a library of DSP functions and more than 150 audio, voice and fusion applications from over 70 partners.

Virtual prototyping
The increased complexity of SoCs has also led to a need for virtual prototyping and Cadence sees its PSpice tool thus being used more as it can handle an entire PCB. As the trend moves from PCBs to large SoCs, PSpice is able to move with this.
“You have large mixed-signal SoCs that consume less power than the PCBs,” said Parag Choudhary, Product Engineer. “These are suitable for automotive, medical, IoT and so on, leading to a trend to shift from PCBs to large SoCs.”
There are, however, a lot of requirements from users. System designers will use PSpice designs to create a requirement that can be handed over to the IC companies. The IC companies then want to integrate that into the design flow. But PCB designers don’t want to mange the design of each model because modelling is an expensive exercise.
“You have all three – system, IC and PCB designers – involved,” said Choudhary. “We wanted to provide something that links all three together. You can work in PSpice and bring it all together.”
This is where the company’s Virtuoso platform comes into its own as IC companies can take PSpice and use it in the virtual IC implementation. This can then be given back to Orcad users for PCB implementation. It provides a virtual prototyping environment for the PCB. “This is responsible for bringing PCBs and IC designers together,” said Choudhary. “We are working with system and IC design companies. It is a new technology, so we have to hold their hands.”
As the CDN Live event celebrates its tenth anniversary – and there was cake – the company is keen to keep its momentum going as designs become more complex. Through both acquisition and development, the aim is to position itself as the design platform of choice for the foreseeable future.