Tanner to demonstrate multi-threaded analogue simulation with an integrated circuit and MEMS design suite running under Microsoft Vista at DATE

The new tool suite will feature a 3D RF extraction tool that uses a field solver technique to calculate interconnect parasitics in three dimensions. The tool performs fast, hierarchical extraction of devices and interconnect, with 2D resistance and 3D capacitance extraction, resulting in a standard SPICE netlist. An integrated routing capability for chip assembly and analogue layout will be introduced at the show. The router works with the current Schematic Driven Layout (SDL) module of L-Edit and will include the ability to route up to 1,000 blocks of arbitrary shape.

The new router is an area router designed to automate the job of routing non-critical analogue signals or doing full chip assembly when connecting up your analogue and digital blocks. Finally, Tanner will be demonstrating its first multi-threaded simulation of the T-Spice simulation tool. This will enable T-Spice to use multiple processors when solving the large matrices during simulation, with potential time saving of up to 60 percent.