Synplicity's latest ASIC Verification Solution Brings Full Visibility to FPGA-Based ASIC Prototyping

Working with popular simulation tools, such as Synopsys' VCS, (see related announcement, Synopsys and Synplicity Establish Alliance to Advance High-Performance ASIC Verification) the Identify Pro solution automatically connects the prototype hardware with an existing software
simulation environment in a transparent and seamless manner for comprehensive RTL code analysis and debug. The Identify Pro software provides initialization of the simulator and automatically creates a test bench from the actual stimulus of the FPGA-based prototype, giving designers a verification solution that is orders of magnitude faster in performance than any other ASIC verification methodology.

Identify Pro ushers in a new era of hardware-assisted verification and it is one of the cornerstones of our ASIC and ASSP verification strategy, said Juergen Jaeger, senior director of ASIC verification marketing at Synplicity. As ASICs become bigger, more costly and more software-centric, it is critical for the design team to be able to effectively detect and analyze bugs that otherwise would be missed until final silicon. The Identify Pro software reduces this risk significantly by giving designers full visibility into their design running at hardware speed in an FPGA-based prototype. In case of an assertion, or other trigger, the design, together with an automatically generated test bench,
is uploaded into a simulator for detailed debug and analysis. By combining the visibility of a simulator with the speed of hardware, the Identify Pro software provides a true breakthrough in ASIC verification.

The Identify Pro software allows ASIC and ASSP designers, using an FPGA-based prototype system, to functionally debug their design at hardware speed, directly in their RTL source code. This allows functional verification for RTL designs that is up to 10,000 times faster than RTL
simulators and enables the use of real-world stimulus, making it an ideal verification platform for applications like networking, audio, video, and all designs with large amounts of software content. Used in conjunction with Synplicity's Synplify Premier physical synthesis tool, the Identify
Pro software enables assertion synthesis into hardware and assertion debug.

The Identify Pro software offers the fastest method of finding errors in an FPGA or ASIC prototype by using live stimulus to quickly reach a trigger condition such as a functional bug or assertion failure. By using advanced triggering capabilities, including assertions that are inserted into the RTL source code, design problems are found that could take a simulator days or weeks to uncover. Once a functional bug or assertion failure is found, the Identify Pro tool's TotalRecall technology is used to initialize a standard software simulator with all signal and state values at a user-defined number of clock cycles prior to the trigger being reached. The complete module state, along with a test bench, is automatically exported to an RTL simulator where the user can replay the sequence and diagnose bugs in the original RTL source code. The Identify Pro product is ideal for ASIC verification teams using FPGA hardware as it allows them to quickly find functional errors in their design. With the coverage of
real-world data and the speed of real hardware, the Identify Pro tool provides a comprehensive verification environment for finding, fixing, and verifying functional errors in FPGA and ASIC designs.

The Identify Pro software, featuring the TotalRecall technology, will be available for early adopters in the third quarter of 2007. Prices range from $34,500 (USD) for a one-year time-based license to $69,000 (USD) for a perpetual, floating license.