SiP & PVS technologies enabled for dense packaging

TSMC’s InFO advanced wafer-level packaging technology provides cost-effective system scaling to increase system bandwidth, while decreasing power consumption and device form factors. Compared to other methodologies, InFO is more suitable for mobile and IoT applications.

In collaborating with TSMC for this enablement, Cadence developed IC packaging technology in Allegro SiP Layout to address InFO-specific design requirements, and provided features that allow designers to meet and verify the design rules, layout structures and metal density requirements of an InFO design. Cadence tailored the mask-generation technology to accurately represent the InFO design structures in GDSII, allowing designers to verify the accuracy of the mask prior to submission to TSMC for fabrication.

“As the demand for mobile and IoT applications grows, the need for advanced packaging options increases as well,” said Keith Felton, Product Management Group Director, PCB Group, Cadence. “Our in-house expertise in IC Packaging design and IC Physical Verification coupled with our experience working with TSMC enables us to develop and deliver specific InFO layout and verification features to meet their manufacturing requirements in design, leading to shorter design cycles and faster time to market.”

“By working closely with us and our lead customers, Cadence was able to address the unique needs of InFO packaging and develop and validate a complete solution,” said Suk Lee, Senior Director, Design Infrastructure Marketing Division, TSMC. “This integrated tool flow bridges the domains of both IC package design and IC manufacturing, ultimately leading to our overall successful broad deployment of the InFO packaging technology.”