Silicon Labs Introduces Online Clock Tree Design Service

Performance-sensitive applications often require a combination of oscillators, clock generators and clock buffers to provide critical reference timing to high-speed SerDes devices, FPGAs, processors, data converters (ADC/DACs) and digital signal processors (DSPs). Not only is individual timing component selection critical, but system-level requirements also need to be taken into account to optimize performance.

Silicon Labs’ online Clock Tree Design Service enables customers to enter their system-level timing requirements using a web-based utility, specifying multiple parameters including the number of clock inputs and outputs, input and output frequencies, signal formats and clock jitter. Silicon Labs’ applications engineering team reviews the requirements and provides a timing architecture optimized for performance, cost and lead time. Timing proposals are provided in just three business days, providing rapid feedback to customers.

“Silicon Labs’ applications team has extensive experience with high-speed PCB design, signal integrity, signal termination, power supply noise rejection and other challenges common to high-performance applications,” said Mike Petrowski, general manager of timing products for Silicon Laboratories. “Our online Clock Tree Design Service enables customers to solicit rapid feedback, accelerating the product development process while reducing risk and ensuring next-generation hardware designs are optimized for system performance.”