Signoff tools have achieved certification from TSMC

The Cadence custom/analogue and digital implementation and signoff tools have been validated by TSMC on high-performance reference designs in order to provide customers with the fastest path to design closure. The Cadence tools in the flow include:

• Innovus implementation system: The solution incorporates a massively parallel architecture that enables increased capacity and a reduced turnaround time. It supports all of the TSMC 10nm design requirements, such as floorplanning, placement and routing with integrated color-/pin-access /variability-aware timing closure, and clock tree and power optimisation.

• Quantus QRC extraction solution: This signoff extraction solution supports both cell-level and transistor-level extractions during design implementation and signoff using one unified foundry-certified techfile. It meets TSMC accuracy requirements for all 10nm modeling features, including multi-patterning, multi-colouring, and built-in 3D extraction capability, and produces the smallest netlist to expedite simulation runtimes.

• Tempus timing signoff solution: This solution offers integrated, advanced process delay calculation and static timing analysis that meets TSMC’s rigorous accuracy standards for the 10nm process. Massive parallelism in computation coupled with 'in-design' signoff Engineering Change Orders (ECOs) in the Innovus implementation system rapidly address signoff closure to minimise ECO iteration time.

• Voltus IC power integrity solution: This SoC power signoff tool is certified for its accuracy in supporting comprehensive electromigration and IR-drop design rules and requirements for the TSMC 10nm process. Together with other Cadence products in the flow, Voltus IC power integrity solution provides a gate-level total power integrity analysis and optimisation solution that helps customers to achieve the best power, performance and area, along with a fast path to design closure.

• Voltus-Fi custom power integrity solution: This SPICE-level accurate, transistor-level tool is used to analyse and signoff analogue, memory and custom digital IP blocks, and create accurate macro models that represent the power grid view of the IP blocks during the SoC power signoff run with Voltus IC power integrity solution. It is certified by TSMC for its accuracy in supporting comprehensive EM/IR design rules and requirements for the 10nm process down to the transistor device level.

• Virtuoso custom IC advanced-node platform: This custom design platform provides the innovative 'in-design to signoff' flows, integrating signoff-quality electrical and physical design checking that is highly correlated to the Cadence TSMC-certified signoff platforms. Customers experience fewer iterations in all design verification categories, which translates directly into increased designer productivity.

• Spectre simulation platform: Spectre circuit simulator, Spectre accelerated parallel simulator, and Spectre extensive partitioning simulator deliver fast and accurate circuit simulation with full support for 10nm device models with self-heating and reliability effects.

• Physical verification system: PVS includes advanced technologies such as pattern matching, interactive DRC and in-design signoff using the Virtuoso custom IC platform and the Innovus Implementation System to significantly reduce iterations and achieve faster design closure.

• Litho electrical analyser: The TSMC API integration with Litho electrical analyser allows Layout-Dependent Effects- (LDE-) aware resimulation, layout analysis, matching constraint checking, reporting on LDE contributions and the generation of fixing guidelines from partial layout to accelerate 10nm analogue design convergence in the Virtuoso custom IC advanced-node platform.