Samsung and Cadence Deliver 20nm Digital Design Methodology

6th June 2012

ES Admin

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Cadence Design Systems, Inc. today announced that Samsung Electronics and Cadence have collaborated to deliver a 20-nanometer design methodology that incorporates double patterning technology for joint customer deployment and internal test chips. The collaboration between Cadence and Samsung brings new process advances for mobile consumer electronics, enabling design at 20 nanometers and future process nodes.

“With our focus on mobile consumer electronics, we needed a more efficient way to create, and help our customers create, differentiated products,” said Dr. Kee Sup Kim, vice president of the System LSI Design Technology team, Device Solutions, Samsung Electronics. “By teaming with Cadence, we have developed a methodology for 20-nanometer design that delivers the benefits of advanced process nodes by utilizing the latest available technologies, such as double patterning.”

Double patterning is a key new approach to lithography that enables higher routing density for advanced process nodes. Double patterning splits each metal layer of designs into two masks for chip fabrication, enabling higher metal density and smaller silicon area for process technologies at 20-nanometers and below.

This announcement marks the latest milestone in a comprehensive multi-year collaboration between Samsung and Cadence to develop ICs at advanced process nodes. The Cadence Encounter RTL-to-GDSII flow, Virtuoso custom/analog flow, and Cadence signoff solutions were qualified for and deployed with Samsung’s 20-nanometer fabrication process.

For the digital parts of the chip, the Encounter Digital Implementation System provided an automated methodology for double patterning-correct placement and routing using its patent-pending FlexColor technology for real-time colorization. The EDI System delivers die-area efficiency and DRC accuracy during placement, optimization and routing. For final signoff, engineers used the Cadence Encounter Timing System, Encounter Power System and QRC Extraction, which has been enhanced to accept multiple extraction values to manage variation in double-patterning alignment.

“Our deep collaboration with Samsung, which began with 32-nanometer designs, continues to bring important advances in chip design and fabrication,” said Dr. Chi-Ping Hsu, senior vice president of research and development, Silicon Realization Group at Cadence. “Samsung’s manufacturing expertise at advanced nodes, combined with our tools and methodologies for 20-nanometer design, was key to the success of this project. We look forward to many more technology advances through collaboration with Samsung to enable customers at the 20-nanometer node and below.”