RTOS support for portfolio of RISC-V-based SoCs

Today’s IoT edge designs are increasing their use of RISC-V to execute time- and mission-critical software applications, often in SoCs where the RISC-V cores are combined with Arm or Intel CPUs on a single SoC. These heterogeneous mixed-core platforms are challenging to debug and optimise, often leading to developer productivity issues that negatively impact product release schedules.

The combination of Green Hills Software’s µ-velOSity RTOS, middleware, hardware JTAG probe, and world-class MULTI development tools provides a single integrated development environment that is purpose-built for debug and optimisation of heterogeneous processor SoC designs where the RISC-V core is either the main general-purpose CPU or is a secondary special-purpose acceleration core alongside the CPU.

“As the drive towards ever more complex multicore applications continues, the combination of security and safety – two similar but very different domains – into a single application, is enabled by our partners at Green Hills Software,” said Tim Morin, Technical Fellow and Marketing at Microchip Technology Inc. “Having µ-velOSity and MULTI available for use by our mutual PolarFire SoC customers makes the development of these highly integrated applications a reality.”

“Any Instruction Set Architecture (ISA) is only as good as the software ecosystem supporting it,” said Rob Oshana, Vice President of Software at NXP Edge Processing Business and Chairman of the Board of Directors at Open Hardware Group. “I’m excited to see Green Hills bringing its leadership in embedded safety and security to the RISC-V community. This will be an enabler of RISC-V technology for automotive and industrial applications and provide robust tools support for developers wanting to innovate using RISC-V instruction extensions.”

Faster Development and Deployment with Superior Quality – The µ-velOSity RTOS’ simple, intuitive API for RISC-V together with its integrated middleware saves significant development time. When combined with the comprehensive, safety-certified, OS-agnostic MULTI development tools, developer productivity is increased, enabling customers to bring higher performing and more reliable products to the market much faster.

Key advantages of MULTI include a single dashboard to view the debugging of heterogenous cores in the SoC, kernel aware debugging, record-setting C/C++ compilers, MISRA-C adherence, and integrated code quality tools for stack performance and run-time errors.

The µ-velOSity RTOS, MULTI development tools, optimising C/C++ compilers and hardware JTAG probe for RISC-V are available today for qualified customers.