Cadence Encounter Digital Technology Provides Ambarella With Big Improvements in Power, Performance and Area

Using the latest Encounter technology, version 11.1, Ambarella saw a 15 percent improvement in performance and a 6.4 percent reduction in power consumption over the prior Cadence technology when designing the encoder/transcoder SoC.

“The complete Cadence Encounter RTL-to-GDSII flow allowed us to tape out a complex 32-nanometer SoC design and achieve significant and meaningful improvements in power, performance and area,” said Chan Lee, vice president of VLSI engineering at Ambarella. “The Clock Concurrent Optimization (CCOpt) technology alone saved us weeks of manual work by allowing us to optimize clocks and datapaths at the same time, while still delivering excellent results in power, performance, and area.”

Ambarella was able to concurrently optimize the initial netlist for power, performance and area using RTL Compiler’s global synthesis approach, which enabled a predictable handoff to EDI System implementation. The new GigaOpt optimization engine inside EDI System produces results faster than traditional optimization engines by harnessing the power of multiple CPUs. In addition, the CCOpt technology unifies clock tree synthesis with logic/physical optimization, resulting in significant power, performance and area improvements. When joined with the integrated signoff-proven QRC Extraction and Encounter Timing System, the full benefits of CCOpt timing optimization are maximized by eliminating timing correlation ECOs, improving time to tapeout.

“Cadence is committed to technology leadership and deep collaborations with foundries and IP providers to enable customers like Ambarella to succeed in very competitive markets,” said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “The Encounter RTL-to-GDSII flow, with many of the latest advanced technologies, enables Ambarella to hit market windows with high-quality products.”