Renesas announces IAR Embedded Workbench support for the SH-2A family

The SuperH architecture is one of the world’s most popular 32-bit cores and IAR Embedded Workbench is one of the world’s most popular compilers and IDEs. This development gives SuperH developers another option to use for their development while adding a significant software performance improvement.

This core, an enhanced version of Renesas’ SH-2 core with a superscalar architecture, has two execution units in the pipeline. Allowing two instructions to be processed concurrently, code can be executed up to twice as fast as the CPU clock. In addition, its Harvard-based architecture ensures that no bus conflicts occur between instruction fetch and data access. The SH-2A also features the addition of an optional Floating Point Unit (FPU), and reaches performance of up to 480 DMIPS and 400 MFLOPS.

The core’s CPU registers are also arranged in “banks”, with the 19 registers being mirrored 15 times. Using this technique, an interrupt subroutine can use a second set of registers leaving the current ones ready for use upon return from the interrupt subroutine. This means that the registers do not need to be popped onto and back from the stack, providing a quicker return from the interrupt subroutine. As a result, the response time to an interrupt request (IRQ) is as quick as a simple branch instruction (or just 30ns).


IAR Embedded Workbench for SuperH is a set of highly sophisticated and easy-to-use development tools for embedded applications. It incorporates IAR C/C++ Compiler, assembler, linker, librarian, text editor, project manager, and IAR C-SPY debugger combined in an integrated development environment (IDE).

The tools from IAR Systems support code generation and project management for all SH-2A and SH-2A-FPU based devices. On-chip debugging in IAR C-SPY Debugger is supported for Renesas E10A-USB probe. The debugger can also run with the built-in instruction set simulator driver. Further third party debuggers can be used due to a wide variety of industry standard output formats generated by the linker.

The IAR C/C++ compiler is renowned across the embedded industry for delivering reliable, high-performance compiled code. Recent benchmarks have proven that more compact and faster code is generated for SH-2A devices by the IAR C/C++ compiler than by competing compilers.


IAR Embedded Workbench for SuperH provides an upgrade path to high performance SH-2A devices for the many users of other Renesas architectures including the H8 and M16C families. The well known development environment and familiar support for embedded programming provided in the build tools can shorten the learning period and speed up the project.