Reducing power consumption and turnaround times

The Innovus Implementation System handles challenging, complex designs and addressed Toshiba’s requirements utilising technologies such as the GigaPlace solver-based placement technology, GigaOpt low power optimisation and CCOpt concurrent clock and datapath optimisation engines.

The Innovus Implementation System is built on a massively parallel architecture, allowing core algorithms to utilise multi-threading and distributed computing to provide Toshiba with a significant capacity improvement and speed-up on industry standard hardware. These advanced capabilities enabled Toshiba to effectively implement its own custom libraries to meet aggressive power and area targets while also reducing P&R turnaround time.

“Reduction of chip size and power consumption is quite crucial for memory controller designs, especially when targeted for mobile applications. Through our intensive collaboration with Cadence, the Innovus Implementation System has proven to be an effective option for our mobile memory controller design,” said Kazunari Horikawa, Senior Manager of the Design Technology Development Department, Mixed Signal IC Division, Storage & Electronic Devices Solutions Company at Toshiba Corporation. “We plan to apply the Innovus Implementation System to other product designs as well, based on the positive results we’ve experienced with our current design.”

“The Innovus Implementation System speeds Toshiba’s implementations by providing a best-in-class place and route system with massively parallel and multi-threaded optimisation engines,” said Dr Anirudh Devgan, Senior Vice President and General Manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Hitting aggressive power and area targets while reducing turnaround time is critical so that Toshiba can deliver its complex memory controller designs to market within tight deadlines.”