Altera Quartus II Software Version 12.1 Accelerates System Development with Enhanced High-Level Design Flows

The latest version strengthens the Quartus II software’s high-level design environment by continuing to ease traditional hardware development tasks so users can maximize productivity while benefiting from the broad range of leading-edge capabilities of Altera devices. Quartus II software version 12.1 bolsters its support for high-level design flows with the inclusion of an SDK for OpenCL, and enhancements to both its Qsys system integration tool and DSP Builder model based design environment. Also included in the latest software release are several enhancements, such as a partial reconfiguration design flow, new intellectual property (IP) cores and expanded support for 28 nm FPGAs and SoC FPGAs. These enhancements further enable customers’ to rapidly design, implement and get to market using Altera devices.



Accelerating System Development with High-level Design Tools



The high-level design tools Altera offers include system-level C-based, IP-based and model-based design entry systems. These tools support and simplify the development of today’s advanced programmable systems, which include CPU cores, digital signal processing (DSP) blocks and multiple IP sub-systems. The addition of an SDK for OpenCL allows system developers and programmers familiar with C to quickly and easily develop high-performance, power-efficient FPGA-based applications using an open high-level programming language. The SDK for OpenCL reduces hardware design complexities and allows software programmers familiar with C to target FPGAs.



Enhancements made to Altera’s Qsys system integration tool and DSP Builder tool provide further design productivity and system performance benefits to users. Qsys features expanded support for industry-standard ARM AXI3 and AXI4 protocols, and DSP Builder provides expanded support for seven different floating point precisions, including IEEE 754 half, single and double precision support. Further simplifying system design, the latest Quartus II software release includes a 100G Interlaken IP core to enable high-speed chip-to-chip packet transfers and a new video trace monitor IP core for video processing applications.



“As FPGAs continue to integrate additional capabilities through silicon convergence, Altera’s development tools can dramatically increase designer productivity by offering higher levels of design abstraction such as OpenCL,” said Alex Grbic, director of software, DSP and IP marketing at Altera. “Altera continues to be at the forefront of delivering industry-leading development tools and IP, providing our customers withthe fastest path from ideas to implemented systems.”



Included in the Quartus II software version 12.1 is the first production release of Altera’s new partial reconfiguration design flow for Stratix V FPGAs. Partial reconfiguration provides the flexibility to change the device’s core functionality on the fly while other portions of the FPGA design are still running. Designers store different functions in external memory and load them into the FPGA as needed, allowing customers to reduce the size of the FPGA used in their system, save board space and reduce power consumption.



The Quartus II software version 12.1 also includes a variety of additional enhancements, including support for new devices. Several new 28 nm Stratix V, Arria Vand Cyclone V FPGAs and SoC FPGAs are supported in this release, including full support for Arria V GZ FPGAs.