Prototyping tool speeds time-to-market

Protium features Palladium flow compatibility, a four times increase in capacity versus the previous generation and support for up to 100m gates. Cadence therefore claim that the tool reduces prototype bring-up time by up to 70% versus competitive solutions, shortening the process from months to weeks. 

Cadence have also considered the importance of low-power analysis and verification of system and SoC signoff criteria, and have expanded the dynamic power analysis beyond CPF support, with verification and debug support for the IEEE 1801 standard in Cadence Palladium XP II.  

Protium and the expansion in dynamic power analysis are claimed to enable system and semiconductor companies in the mobile, consumer, networking and storage industries to address important design challenges such as early software bring-up and reduced power consumption.

"The ability to use the same bring-up flow for Palladium emulation and Protium rapid prototyping, allows our design teams to switch seamlessly between the two execution engines, which reduces the prototype bring-up time from months to weeks compared to traditional FPGA-based prototyping approaches,” said Hideya Sato, Deputy Executive General Manager, Global MONOZUKURI Division, Information & Telecommunication Systems Company, Hitachi. “Additionally we expect to improve overall development productivity by extending the use of Protium rapid prototyping platform to the area of hardware/software co-verification.”

“The growing need for software and hardware verification continues to drive the use of FPGA-based ASIC prototyping, from emulation and prototyping to mass production applications,” said Arun Iyengar, Vice President, A&D, ISM and TM&E markets for Xilinx. “Cadence’s approach to unify hardware verification using Palladium emulation and software development using Protium prototyping will further streamline the customer’s time to market while improving product quality.”