Processor trace support announced for RISC-V products

Five core vendors have already announced their support for the new trace specification, which is a key function for software developers using any processor; its delivery is an important step forward in the development of the RISC-V ecosystem.

RISC-V is an open source instruction set architecture, initially developed by UC Berkeley but now being more widely adopted. UltraSoC is a member of the RISC-V Foundation, and plays an active role in growth of the surrounding development ecosystem. Processor trace functionality – which allows the behaviour of a programme to be viewed in detail, instruction-by-instruction – is a key must-have for software developers.

“RISC-V is a great architecture: but an architecture is not enough,” said Rupert Baines, UltraSoC CEO. “Customers need the whole ecosystem – an ecosystem that puts designers in control and empowers innovation. UltraSoC is aiming to play a major role in that with our debugging and development IP, and processor trace for RISC-V is a significant supporting pillar in that effort.” UltraSoC is working with major RISC-V core vendors including Andes, Codasip, Roa Logic, SiFive and Syntacore, with the intention of submitting a proposed processor trace format to the RISC-V Foundation later in 2017 as the basis of the open source standard implementation.

Charlie Hong-Men Su, PhD, CTO and Senior Vice President of R&D, Andes Technology, commented: “Our AndeStar V5 architecture, a superset of RISC-V, gets a lot of interest from customers due to Andes’ track record of two billion unit shipment served by rich product solutions and services as well as RISC-V’s growing ecosystem. Andes welcomes continuous strengthening of the latter such as the important announcement of a commercial processor trace functionality from UltraSoC.”

On behalf of Codasip, the company’s CEO, Karel Masarik, said: “As more of our customers adopt RISC-V, the need for a rich standardised ecosystem around deployment and debug is becoming a necessity. Getting these ecosystems in place is key to ensuring RISC-V becomes the first choice of development teams everywhere. We are excited to integrate the proposed trace standard into our broadly adopted Codix-Bk RISC-V processor IP and tools.”

Richard Herveille, Managing Director, Roa Logic, added: “Processor trace is what’s really missing from the RISC-V ecosystem from a debug standpoint, and UltraSoC taking the lead is great. As a founding member of the RISC-V Foundation, we’re delighted to see this significant strengthening of the RISC-V ecosystem.”

“As the original inventors of the RISC-V ISA, we at SiFive have been delighted to see the rapid growth of the RISC-V ecosystem,” said Jack Kang, Vice President of product and business development at SiFive. “We’ve made adoption of SiFive Coreplex IP straightforward and easy with our ‘study-evaluate-buy’ purchase process, and the addition of commercial processor trace support from UltraSoc will make RISC-V adoption even easier.”

Alexander Redkin, CEO, Syntacore, said: “We’re delighted to be working closely with UltraSoC to strengthen the RISC-V ecosystem. We believe that a strong, mature debug infrastructure is a key necessity in the success of RISC-V; the addition of commercial-grade RISC-V processor trace is a big step forward and we are happy to add this much sought after feature to our SCRx cores family offering.”

UltraSoC’s semiconductor intellectual property (SIP) simplifies development and provides valuable embedded analytic features for designers of SoCs (systems on chip). SemiCo Research has estimated that, by using UltraSoC technology in their development flow, chip makers can double the profitability of many projects, and cut development costs by a quarter. The company has a dozen high-profile licensees, including HiSilicon (Huawei), Imagination Technologies, Movidius (now Intel), and Microsemi.

UltraSoC’s partners include Andes, ARM, Baysand, Cadence/Tensilica, CEVA, Codasip, Lauterbach, MIPS, Roa Logic, Syntacore and Teledyne LeCroy. UltraSoC’s implementation of RISC-V processor trace functionality will be available in Q42017.