Process technologies to facilitate HPC design creation

As part of the collaboration, the Cadence digital, signoff and custom/analog tools have achieved the latest Design Rule Manual (DRM) and SPICE certification for the TSMC five nanometre and seven nanometre+ processes, and the corresponding process design kits (PDKs) are now available for download. Customers using Cadence’s implementation, signoff and custom/analog tools are already in production with seven nanometre+ projects, and there are multiple design projects underway with early five nanometre customers.

Cadence delivered a fully integrated digital implementation and signoff tool flow, which has been certified by TSMC for the latest versions of the five nanometre and seven nanometre+ processes. For the seven nanometre+ process, the Cadence full-flow includes the Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution and Physical Verification System (PVS). For the five nanometre process, the Cadence certified tools include the Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution and Voltus-Fi Custom Power Integrity Solution.

Cadence digital and signoff tools optimised for TSMC’s five nanometre and seven nanometre+ process provide EUV support at key layers and associated design rules that enable customers to achieve power, performance and area (PPA) savings at these advanced nodes. Some of the newest enhancements for the five nanometre and seven nanometre+ process include via pillar-aware synthesis and feed forward guidance with the Genus Synthesis Solution as well as a pin-access control routing method for cell electromigration (EM) handling and statistical EM budgeting support.

The Cadence-certified custom/analog tools for the latest versions of the TSMC five nanometre and seven nanometre+ process technologies include the Spectre Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre RF Option and Spectre Circuit Simulator, as well as the Virtuoso custom IC design platform, which consists of the Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso ADE Product Suite and Virtuoso Integrated Physical Verification System. The Layout-Dependent Effect (LDE) Electrical Analyser is also certified for seven nanometre+, and the collaboration on five nanometre is ongoing.

By continually enhancing design methodologies and capabilities included with the Virtuoso Advanced Node Platform for TSMC’s advanced-node processes, customers can achieve better custom physical design throughput versus traditional non-structured design methodologies via the advanced capabilities in the Virtuoso and Spectre tools.

The Virtuoso Advanced Node Platform methodology consists of features and functionality required for creating five nanometre and seven nanometre+ designs including mixed-signal functional verification, reliability analysis and an accelerated custom placement and routing methodology, which enables customers to improve productivity and meet power, multi-patterning, density and EM requirements. Cadence also introduced new features including end-to-end constraint support, dummy insertion and advanced MIMCAP support specifically for the five nanometre process.

In addition to the tools certified for TSMC’s five nanometre and seven nanometre+ process technologies, the Liberate Characterisation portfolio and the Liberate Variety Statistical Characterisation Solution have been validated to deliver accurate Liberty libraries including advanced timing, noise and power models. The solutions utilised innovative methods to characterise Liberty Variation Format (LVF) models, enabling accurate process variation signoff for low-voltage applications and to create EM models enabling signal EM optimisations and signoff.

“Our five nanometre process has matured to a great degree with customers doing early design starts, while our seven nanometre+ technology is production ready and actively in use with mutual customers,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “By collaborating closely with Cadence, we’re enabling customers to deliver innovations using our latest technologies and the Cadence certified tools and flows.”

Dr Chin-Chi Teng, Senior Vice President and General Manager of the Digital and Signoff Group at Cadence, added: “We’ve continued our close collaboration with TSMC on advancing five nanometre and seven nanometre+ FinFET adoption by providing customers with access to the latest technical capabilities for advanced-node design creation. Based on aggressive new R&D optimisations and performance improvements to our digital and signoff and custom/analog tools, customers can deliver innovative, reliable end products in their respective markets within tight timelines.”