Toshiba - Physical layer and protocols provide complete MIPI IP solution for SoC development

Toshiba’s MIPI D-PHY is a bi-directional, low-power, high-speed physical layer to which various protocols can be added dependant on application requirements. At present MIPI-compliant protocols from Toshiba include CSI-2 (Camera Serial Interface 2), DSI (Display Serial Interface) and UniProSM (Unified Protocol).

Compliant with the MIPI D-PHY version 0.92 specification, Toshiba’s MIPI D-PHY provides a re-usable physical layer with support for one to four data channels and a single clock channel. The same D-PHY can be used to for high-speed serial communications in high speed (HS) mode and with single-ended transmission lines in low power (LP) mode. In HS mode the MIPI D-PHY can deliver speeds up to 1Gbps (depending on technology and implementation) through an advanced, scalable source-synchronous, differential SLVS transceiver. In low power (LP) mode the D-PHY provides single-ended transmission at speeds to 10Mbps.

Toshiba’s CSI-2 protocol provides the basis for low-pin-count interfaces between camera modules and, for example, the system host. Data rates as high as 4Gbps enable new camera features and support sensor resolutions beyond 10Mpixel. The Toshiba DSI is a higher layer protocol with error correction that supports solutions for display-related data communication. DSI supports both ‘smart’ (buffered) and ‘video mode’ (unbuffered) display panels. UniPro 1.0/1.1 is PHY-independent and provides a single, unified reliable protocol that can be used across several applications including cameras, displays and device communication interfaces. UniPro offers high-speed communications, error correction for reliability and low energy per transferred bit.

The new MIPI-compliant IP supports the requirements for low-power, low noise generation and high noise immunity demanded by mobile phones. The D-PHY is based on 1.2V supplies and, depending on the application, operational power and standby power are in the mW and µW range respectively.

Additional IP for MIPI-based designs includes optional PLL, lane control and interface logic. Toshiba will continue to develop solutions for future MIPI protocols as they become available.

The MIPI D-PHY will scale across existing and future semiconductor process technologies and Toshiba’s MIPI solutions have already been fully silicon-proven in the company’s own application specific standard products (ASSPs). Based on its advanced 90nm, 65nm and 40nm CMOS ASIC technologies, Toshiba MIPI-compliant ASSPs include devices for display sub-systems as well as camera applications.

Designers at Toshiba’s European LSI Design and Engineering Center (ELDEC) are available to provide full technical support, advice and guidance relating to the deployment of SoCs incorporating MIPI functionality.