Performance Breakthrough for HIL Simulation

8th March 2010

dSPACE Ltd

ES Admin

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dSPACE has given its real-time systems a new heart. The new quad-core DS1006 Processor Board has an AMD Opteron™ 2.8 GHz processor to boost the power of HIL simulation. Large models can be distributed easily across the four cores of the quad-core processor and executed synchronously. So numerous models that formerly required a system of several processor boards can now run on a single DS1006. On every core, the performance and processor-internal communication of the new DS1006 provide model execution that is up to 60% than its predecessor.

This increase in speed is particularly useful for computing very detailed, CPU-intensive models, such as for gasoline engines with variable valve timing and for diesel engines with in-cylinder pressure measurement. The high computing speed is also indispensable in the HIL simulation of hybrid drives, because some of the tasks for electric drives have extremely short cycle times and require their own processor core.

Cases that required several single-core DS1006 boards in the past will frequently be handled by one quad-core DS1006 Processor Board in the future. This not only makes the HIL simulator more cost-effective, but also creates greater freedom for extensions.
To increase performance even further, it is also possible to build systems by connecting several quad-core DS1006 Boards, just as with any other dSPACE multiprocessor system. This way, users can tailor the performance to their requirements – whether they “only” want to process large, CPU-intensive models, or need the modularity of multiprocessor systems to build a virtual vehicle from the test systems for individual ECUs or vehicle domains.

Real-Time Interface for Multiprocessor Systems gives users the convenience to configure their systems with any combination of multiple cores and/or processor boards they like. The same user interface is used in all cases: to partition models for optimum utilization of the processor cores; and to define and specify the communication channels for data transmission between the cores of the quad-core DS1006 boards as well as between processor boards.