PCIe clock buffers designed for next-gen servers and data centres

Each buffer is a suitable complement to chipsets where distributed clocks are required across several peripheral components, such as Central Processing Units (CPUs), Field Programmable Gate Arrays (FPGAs) and Physical layers (PHYs) in data centre servers and storage devices, along with many other PCIe applications.

The devices’ low additive jitter of approximately 20 femtoseconds (~20fs) far exceeds the DB2000Q/QL specification of 80 femtoseconds (80fs). This provides designers large margins to meet tight timing budgets while achieving increasing data rates. These devices will minimise jitter when distributing clocks to up to 20 outputs, thereby maintaining the integrity and quality of the clock signal through the buffer.

The new buffers achieve low power dissipation and contribute significant savings to power budgets by using Low Power High Speed Current Steering Logic (LP-HCSL). Compared to standard HCSL, LP-HCSL consumes one third of the power, leading to a significant decrease in power consumption.

This feature also gives customers the ability to drive longer traces on their board, improving signal routing while reducing components and board space. The ZL40292, for example, can eliminate up to 80 termination resistors (four per output) compared to traditional HCSL buffers.

The ZL40292 and ZL40293 are available now for sampling and in volume production in 72-pin 10x10mm QFN packages. The ZL40294 and ZL40295 are available now for sampling in the 80-pin 6x6 QFN packages.