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Juniper Networks Selects RealTime Designer from Oasys for Next-Generation Networking Chip Designs

18th June 2010

ES Admin

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Oasys Design Systems today announced that Juniper Networks® has selected RealTime Designer™, a revolutionary new Chip Synthesis™ platform, for the design of its next-generation networking chips. “After a thorough evaluation, we determined that RealTime Designer offers high-quality results and performs very well in our environment,” said Debashis Basu, vice president for Silicon Development at Juniper Networks. “It is a great tool that fits a very real performance need in today’s EDA market.”

Juniper Networks will incorporate RealTime Designer into its design flow. Terms of the agreement will not be disclosed.

“We are delighted that Juniper Networks has chosen RealTime Designer for its leading-edge chip designs,” remarked Paul van Besouw, Oasys’ president and chief executive officer. “There is an ongoing effort for design teams to scale for next-generation designs, and improve productivity. Juniper’s designers have a superb track record of designing some of the most challenging chips, which has helped to establish Juniper as the industry leader in the networking world.”

RealTime Designer is the first design tool for physical register transfer level (RTL) synthesis of 100-million gate designs. It features a unique RTL code placement approach that eliminates unending design closure and iterations between synthesis and layout.