Autorouter and layout device generator from Tanner EDA speeds up analogue and mixed-signal ASIC design

SDL Router is an automatic routing engine integrated directly into Tanner EDA’s Schematic Driven Layout (SDL) software. It speeds layout by automatically routing non-critical nets while allowing the designer to focus on routes that require expensive hand craftsmanship for performance or addressing analogue-sensitive nets or parts of nets. The router is interactively controlled by a layout engineer. It natively uses the routing geometry created by the user, and runs on all or a specified subset of nodes on each pass. Users can manually route part of a net and have the router automatically finish routing the net. Because of the router’s integration with Tanner EDA’s SDL software, users can easily highlight and rip up nodes, manage the manual and automatic routing status, and implement Engineering Change Orders (ECOs).

DevGen, coupled with SDL, takes productivity to a new level. DevGen allows analogue layout designers to become more productive by automating much of the tedious task of laying out the devices. DevGen provides parameterised layout generators that are easily configured for any process to help ensure error-free layout. By using the DevGen wizard and answering a few questions about the layers involved and the Design Rule Checks (DRCs), designers can create parameterised cells of common devices without having to write code. DevGen includes layout generators for capacitors, resistors, inductors, MOSFETs, and diodes.

SDL Router and DevGen increase the speed and quality of custom layout and encourage good design practices by keeping close synchronisation between the schematic and the layout. SDL improves productivity by automating instancing of cells and parameterised devices and placement quality by displaying real-time node flylines. It also helps avoid routing congestion and tracks an engineer’s progress to help manage workflow.

Version 14.10 of Tanner Tools Pro and HiPer Silicon also includes improved Verilog-A integration to reduce analogue simulation runtimes, when simulations include digital blocks. HiPer Verify runs Calibre and Dracula foundry files natively, without conversion or modification as well as Assura foundry files natively. Safe Operating Area (SOA) checks in T-Spice have been added, so models stay valid and circuits operate correctly. The software’s interactive DRC displays violations in real time during layout editing that help layout engineers create compact, error-free layouts the first time. Spacing distance is displayed in real time while the layout is edited and can prevent editing from getting closer than the minimum distance.