Mentor Graphics Teams with OpSIS Foundries and Lumerical Solutions on PDK Development for IME Silicon Photonics Process

After almost of year of development and testing by the combined team of OpSIS, Mentor and Lumerical, the OpSIS team has demonstrated a prototype full design implementation and verification flow for the IME silicon photonics process. This flow uses the Mentor® Pyxis® custom IC design platform for schematic capture and schematic-driven layout, along with the Mentor Calibre® nmDRC™ and Calibre nmLVS™ tools with detailed parameter checking for physical verification of the design. This prototype flow is available for use by design teams who participate in an OpSIS MultiProject Wafer design workshop.



“We are extremely pleased with the industry collaboration and support OpSIS had received in developing a PDK for use by silicon photonics designers,” said Michael Hochberg, co-founder and director, OpSIS. “By working together, we are making silicon photonics a reality for multiple applications, research efforts, and companies that would not be able to do such work independently.”



The OpSIS PDK also relies on technology from Lumerical Solutions for optical simulation that is set up to let users create and manage Lumerical INTERCONNECT projects inside the Pyxis environment. Lumerical INTERCONNECT is used to provide system level optical analysis of integrated silicon photonics circuits. Compact model development work is ongoing using Lumerical’s FDTD Solutions, MODE Solutions and DEVICE to complement the experimental data.



“The simulation of photonic circuits inside an EDA-style flow is extremely challenging so we are excited to reach the critical step of exporting a circuit to INTERCONNECT for simulation,” said James Pond, PhD, chief technology officer, Lumerical Solutions. “We look forward to collaborating with our partners and also the end users to ensure that this design and simulation flow meets their needs in the future.”



Within the Pyxis custom IC design platform, the OpSIS PDK currently supports call-back driven photonic PCells that can be quickly assembled using connectivity-driven waveguide routing with radial and adiabatic bends, as well as S-bend support. Design rule checking is done with the Calibre nmDRC tool using out-of-the-box SVRF rules with special considerations for silicon photonic structures, along with the Calibre nmLVS tool for device checking that is similar to other high-volume design flows used in the industry. Tiling and mask preparation is done using Calibre SmartFill in conjunction with the Calibre DESIGNRev™ tool. Mentor has also partnered with OpSIS to ensure access to design tools so this does not become a barrier to the development of silicon photonics test chips.



“Silicon photonics is becoming an important design enabler, especially for data communications. As this technology finds its way into more and more chips, it is extremely important that traditional EDA providers partner with the companies providing dedicated photonics tools and with foundries supporting silicon photonics. We are very pleased to be part of this collaboration,” said Linda Fosler, director of marketing, Deep Submicron Division, Mentor.



Want to learn more about what is happening in silicon photonics? Mentor and OpSIS are presenting their work and its application in a session in the Mentor booth at DAC titled ‘Preparing for Pervasive Photonics.’ The Design Automation Conference (DAC) is held in Austin, TX, June 2 - 5. For event information, please go to the Mentor DAC web site.