Mentor Graphics supports 16FFC FinFET processes

Moreover, the Calibre offering has been extended on additional established TSMC processes in support of the growing IoT (Internet of Things) design market requirements.

The AFS Platform, including AFS Mega simulation, has been certified for the TSMC 16FFC FinFET and the TSMC 7nm FinFET process technologies through TSMC’s SPICE Simulation Tool Certification Program. The AFS Platform supports TSMC design platforms for mobile, HPC, automotive, and IoT/wearables. Analogue, mixed-signal, and RF design teams at leading semiconductor companies worldwide will benefit from using Analogue FastSPICE to efficiently verify their chips designed in 16FFC and 7nm FinFET technologies.

Mentor’s Calibre xACT extraction offering is now certified for the TSMC 16FFC FinFET and the TSMC 7nm FinFET process technologies. Calibre xACT extraction leverages its built-in deterministic fast field-solver engine to deliver needed accuracy around three-dimensional FinFET devices and local interconnect. Its scalable multiprocessing delivers sufficient punch for large leading-edge digital designs. In addition, both companies continue extraction collaboration in established process nodes, with additional corner variation test cases and tighter criteria to ensure tool readiness for IoT applications.

The Calibre PERC reliability platform has also been enhanced to enable TSMC 7nm customers to run point-to-point resistance checks at full chip. This greater capacity allows customers to quickly analyse interconnect robustness at all levels (IP, block, and full chip) while verifying lower resistance paths on critical Electrostatic Discharge (ESD) circuitry, helping ensure long-term chip reliability. Likewise, Calibre Multi-Patterning functionality has been enhanced for 7nm, including new analysis, graph reduction and visualisation capabilities which are essential to customers designing and debugging this completely new multi-patterning technique.

The Calibre YieldEnhancer ECOFill solution, initially developed for 20nm, has now been extended to all TSMC process nodes from 7 to 65nm. Designers at all process nodes will now be able to minimise fill runtimes, manage fill hierarchy, and minimise shape removal when implementing changes to the initial design.

Mentor’s Nitro-SoC P&R platform has also been enhanced to support advanced 7nm requirements, such as floorplan boundary cell insertion, stacking via routing, M1 routing and cut-metal methodology, tap cell insertion and swapping, and ECO flow methodology. Certification of the flow integration of these N7 features are on-going. For 16FFC, the needed tool features have been validated by TSMC, and Mentor is optimising its correlation with sign-off analysis.

“Today’s chip design teams are looking at different process nodes to implement their complete solution,” said Joe Sawicki, Vice President and General Manager of Mentor Graphics Design-to-Silicon Division. “By working with TSMC, Mentor is able to provide mutual customers with a single solution that is not only certified, but also includes the latest tool capabilities, for whichever TSMC process node they choose.”

“TSMC’s long-standing collaboration with Mentor Graphics enables both companies to work together effectively to identify new challenges and develop innovative solutions across all process nodes,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “The Mentor Analogue FastSPICE Platform, AFS Mega, and Calibre xACT tools have successfully met the accuracy and compatibility requirements for 16FFC and 7nm FinFET technologies. That certification, along with the Calibre Platform’s provision of fast, accurate physical verification, and extraction solutions critical to 7nm, ensures mutual customers they have access to EDA tools that are optimised for the newest process technologies.”