Mentor and ASSET Deliver IJTAG Automated Chip-to-System-Level IP Integration

“In order for the IJTAG standard to be effective, system-on-a-chip (SoC) and PCB designers, as well as system-level manufacturing engineers, need an ecosystem of support from semiconductor IP providers, EDA tool providers and hardware/software debug, validation and test tool providers like ASSET,” said Kent Zetterberg, ASSET’s IJTAG product manager. “We’re working with Mentor to provide a seamless flow based on IJTAG from the IC design environment to the SoC and PCB debug, validation and test phase.”

“We are now seeing widespread interest in the IJTAG standard within our customer base,” said Stephen Pateras, product marketing director at Mentor Graphics. "Ensuring interoperability with key partners like ASSET will help maximize the benefit to our customers when adopting this new technology and standard. At this year’s International Test Conference, Mentor and ASSET will demonstrate a design flow with full PDL/ICL interoperability to be delivered later in the year, synchronized with ratification of the IEEE P1687 IJTAG standard.”

Tessent IJTAG combined with ScanWorks lets engineers access the operational and diagnostic features of all IP blocks in the design from a top-level interface, greatly simplifying the job of integrating the hundreds of IP blocks in a typical system. Interoperability between the two solutions revolves around the IEEE P1687 standard’s Instrument Connection Language (ICL) and Procedural Description Language (PDL).

The Tessent IJTAG tool reads ICL and PDL code delivered with third-party IP blocks and verifies that it is IEEE P1687 (IJTAG)-compliant. It then generates a logic network and associated ICL to integrate all the IP blocks in a design and processes the PDL for each IP to create composite chip-level PDL. The ScanWorks product then reads chip-level ICL and PDL for use in chip debug and also retargets the PDL to a board or system level interface.