LeCroy Introduces Simulation Design Verification Tool for PCI Express 3.0 Protocol Analysis

Synopsys, a world leader in software and IP for semiconductor design and manufacturing, will be the first company to support the SimPASS tool through its DesignWare® Verification IP for PCI Express. Users of Synopsys’ DesignWare Verification IP for PCI Express will be able to export simulation vector files and use the analysis capabilities of SimPASS PE.

SimPASS PE for PCI Express is the first tool to be available in the new SimPASS product line. SimPASS allows RTL simulation vector files (that describe PCI Express 3.0 I/O traffic in the pre-silicon phase) to be displayed and analyzed in the same way as hardware-derived trace files in the post-silicon phase. By extracting features that show potential flaws in data and transaction packets from the I/O stream, SimPASS enables developers to more completely test and debug the logic design before committing the design to silicon, a major advance in eliminating design flaws that can cause expensive and time-consuming redesign. Major issues facing PCI Express 3.0 developers, such as flaws in power state transitions in the LTSSM and improper credit flow exchanges, can be quickly discovered, tracked to their source, and resolved, resulting in significantly faster time-to-market and lower development costs in new product development.

“LeCroy’s SimPASS PE provides designers with a new way to observe and analyze PCI Express-based I/O traffic,” said Scott Knowlton, Product Marketing Manager of Synopsys. “The DesignWare Verification IP for PCI Express, used in conjunction with the SimPASS protocol analysis capability boosts design productivity and helps ensure that protocol errors and performance issues are discovered in simulation before going to silicon.”

SimPASS works by importing raw PCI Express symbol traffic as captured in an RTL simulation. Developers can export RTL simulation vector files from leading electronic design automation (EDA) PCIe® compliance tools, or from their own internally developed RTL testbench. The symbol traffic files are directly analogous to a trace file captured from hardware, and can be analyzed by SimPASS, helping to determine potential protocol errors. This provides important advantages in identifying and troubleshooting logic design flaws during the simulation and functional verification process, by using the powerful data displays and “drill down” capabilities of the CATC Trace displays in quickly locating the source of each error. The ability to track down errors using familiar data displays and error identification tools makes the error resolution process simpler and easier for the engineers involved. During any redesign cycle, fixes for bugs (identified in the previous cycle using LeCroy's PETracer trace analysis software) can be verified by testing the fixes during simulation using the SimPASS software.

“We have taken an important step in providing a comprehensive analysis solution for chip developers,” said John Wiedemeier, Product Marketing Manager of LeCroy’s Interconnect Communications Group. “SimPASS will bring a new level of protocol awareness to the simulation environment and enable engineers to catch and resolve a multitude of errors that would normally have been missed with today’s simulation tools.”

LeCroy’s PCI Express protocol test family includes the newly announced PCIe 3.0 (Gen3) Summit™ T3-16 protocol analyzer supporting up to x16 lanes, the Edge™ T1-4 for PCIe 1.0 support with lane widths up to x4, the PETracer™ ML Analyzer and Exerciser for PCIe 1.0 support with lane widths up to x8, and the Summit T2-16 Analyzer and Summit Z2-16 Exerciser for PCIe 2.0 (Gen2) support with lane widths up to x16. LeCroy will show a demonstration of SimPASS on February 2-3 at booth No. 109 at DesignCon at the Santa Clara Convention Center.