Lattice Updates Software Design Tools for Hot Swap Control and Power Management

Lattice Power Manager II devices integrate programmable analog and PLD technologies to support digital power management solutions. As more digital management functions are integrated, the verification step in the design flow depends on robust simulation technology. The PAC-Designer 5.2 software provides a new VHDL or Verilog HDL export feature to extract simulation models of the embedded PLD block featured on all Lattice Power Manager II family devices. This allows for functional verification of sequence and supervisory logic by the Aldec Active-HDL Lattice Web Edition simulator.

By adding Active-HDL to the PAC-Designer software verification flow, Lattice has provided a high-quality simulation and verification solution for their power management product line. Logic targeted to the PLD block of a Lattice Power Manager II family device can now be simulated with Aldec's IEEE standard VHDL/Verilog single or mixed language simulators, said Dave Rinehart, Vice President of Marketing, Aldec, Inc. As an extension to our current OEM agreement, all Aldec simulation products, including the Active-HDL Lattice Web Edition, now include support for the Lattice Power Manager II family at no cost to Lattice customers.

Power Manager II devices are commonly used to integrate discrete ICs for power management such as voltage supervisors, reset generators, watchdog timers and Hot Swap controllers. By adding HDL export features to PAC-Designer software, power supply sequencing, reset signal distribution, and other digital logic integrated into a Power Manager II device can be modeled with IEEE industry standard Verilog HDL or VHDL. PAC-Designer and Active-HDL Lattice Web Edition software can be downloaded for free from: www.latticesemi.com/products/designsoftware/pacdesigner

PAC-Designer software remains an important reason why engineers continue to adopt Lattice power management and programmable clock devices. Our design environment is very easy to use and it offers both analog and digital specialists the ability to complete designs quickly and confidently, said Chris Fanning, Lattice Corporate Vice President and General Manager of Low Density and Mixed Signal Solutions. PAC-Designer 5.2 software supports the expanded performance of the POWR1014/A-2 and ispClock 5400D devices, which lowers cost and provides more hardware flexibility. The PAC-Designer interface to Active-HDL allows designers to use one of the market's most effective EDA tools for HDL simulation.