Lattice -Helion Compression IP Core

The IP core is seamlessly scalable from 500Mbps to over 3Gbps in the LatticeECP3 device, and may be used in typical networking applications at either Layer 2 or Layer 3. The IP core uses a very robust and mature implementation of the LZRW lossless compression algorithm, which has been in production use by Helion customers for more than five years.

Additionally, the LZRW lossless compression core is available separately for applications more suited to embedded implementations. The core is available in Compress only, Expand only, or combined Compress/Expand versions, and supports data rates over 500Mbps.

Helion is best known for its comprehensive suite of solutions implementing AES (the Advanced Encryption Standard). Helion was first to market in 2000 with a wide range of commercial AES cores when the standard was not widely known. AES is now pervasive and found in many standards, covering commercial, military and government applications. Helion offers a broad range of solutions carefully tailored to each requirement and engineered for optimal use in FPGAs, based on more than a decade of experience with AES. In each case, options allow the user to trade-off resources and performance to achieve an elegant and efficient solution.

The Helion Fast Hash core family implements the NIST-approved SHA-1, SHA-256, SHA-384 and SHA-512 secure hash algorithms compliant to FIPS 180-3 and the legacy MD5 hash algorithm compliant to RFC1321. These high performance secure hash cores are available in single or dual-mode versions and have been designed specifically for use in the LatticeECP3 FPGA family. Additionally, for implementations that are more resource-constrained relative to performance, a super compact “Tiny” Hash core is also available that offers full multi-mode support plus a rich feature set.

For accelerating Public/Private key protocols, the Helion Modular Exponentiation core offers an easy to use and highly scalable solution. The core is available in several versions, each sharing an identical interface but differing in the number of clock cycles required to perform each operation. .

“We are pleased to make a significant number of our Data Security and Compression IP Core products available for use with the LatticeECP3 FPGA family,” said Graeme Durant, CEO of Helion Technology, U.K. “Our quality IP cores have been crafted to achieve their very best performance in the LatticeECP3 FPGA, and thoroughly tested to ensure compliance with any associated standard.”

“Our goal with Helion Technology is to provide access to a world class, mature and robust Compression and Encryption IP portfolio that enables our customers to jumpstart their FPGA-based development,” said Lalit Merani, Senior Manager of Product Marketing at Lattice Semiconductor. “With a broad array of IPs supported both a la carte as well as integrated into system IPs, our mid-range LatticeECP3 FPGA family provides the lowest power, highest value solution for our customers.”