IP supports Ethernet at speeds of 25G, 50G, 100G & 400G

30th March 2015

Siobhan O'Gorman

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Semtech has announced a collaboration with MorethanIP, linking the IP from each party to produce a complete layer 1/layer 2 solution for IEEE 802.3bj, the recently ratified standard supporting 100G backplane applications.

In addition, the added capabilities provide solutions for new industry standard 25GbE and 50GbE configurations, and for applications compliant with the developing 802.3bs 400GbE standards with CDAUI-16.

More customers are developing optimised solutions to support Big Data applications and the IoT. These customers are building data centres that benefit from SOC/ASICs that support Ethernet standards like IEEE 802.3bj, 802.3bm and 802.3by. The emerging set of standards leverage the serial rate of 25G per lane. By working closely together, Semtech and MorethanIP now offer a working solution for customers who wish to deploy I/Os that support these standards on their system-level ASICs.

“We recognise that there are many customers who want a combined MAC and PHY solution for the set of standards that use the 25G serial data rate,” said Francois Balay, President, MorethanIP. “Working with Semtech to validate our joint solution allows customers to deploy our IP with confidence in their ASIC designs for legacy 10GbE, stable 40/100GbE, emerging 25/50GbE and future 400GbE applications.”

“Customers expect that they can get IP from two vendors to work together on their ASIC/SOC designs, and our announced partnership with MorethanIP formalises the working relationship we have had with them for many years, servicing many companies,” said Kevin Walsh, Director, Worldwide Marketing, Snowbush IP brand. “Now, as the industry moves to new standards using 25Gb/s serial lane rates, like 802.3bj, 802.3bs, 802.3bm and 802.3by, they can deploy our joint IP with the confidence that two vendors support one combined solution.”

The IP-C2 platform GDS is available immediately on TSMC 28nm HPM/HPC. MorethanIP’s MAC layer IP is available immediately as RTL and can be synthesised to any process node. The companies are working on a reference design kit that will be available soon. Pricing depends on configuration and the number of instantiations in a design. Silicon results are available for review.