Implementation system certified on 16nm FinFET process

Additionally, Cadence and TSMC are collaborating on the certification of the Innovus Implementation System on the 10nm FinFET process. The certification for the latest version of 10nm DRM and SPICE models is currently on target for completion in June 2015.

The Innovus Implementation System is a next-gen physical implementation tool that enables SoC developers to deliver high-quality designs with highly competitive Power, Performance and Area (PPA), while accelerating time to market. The tool provides key technology for the 16FF+ process and supports floorplanning, placement and routing with integrated colour-/pin-access-/variability-aware timing closure, clock tree and power optimisation.

TSMC’s certification of Innovus Implementation System capabilities include GigaPlace placement technology, which improves electrical and physical design closure, as well as integration with Cadence Quantus QRC Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, and Physical Verification System, providing a fast path to design closure.

“The Innovus Implementation System enables high quality results and fast path to design closure with its breakthrough placement and optimisation capabilities and multithreading,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “TSMC’s certification of the Innovus Implementation System gives customers more confidence that their 16FF+ designs can meet aggressive PPA targets so they can deliver high-quality designs to market faster. We continue to closely partner with TSMC on the advancement of 16FF+ designs so our customers can stay at the forefront of silicon technology.”

“The Cadence and TSMC R&D teams collaborated closely on the certification of the Innovus Implementation System, and we are committed to enabling our mutual customers to deliver innovative, advanced-node designs to market,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “With this certification, designers can achieve rapid design closure while reaping the benefits of higher performance and lower power consumption on TSMC’s 16FF+ process.”