Implementation system achieves V0.9 certification

The Innovus implementation system offers customers key technologies needed to stay in front of the competition using the TSMC 10nm process. Some of the technology capabilities include GigaPlace solver-based placement technology, the pin-access-aware feature ensures the cells are placed in accordance with 10nm orientation, colouring and edge-constraint requirements to avoid downstream routing issues, while enabling designers to meet aggressive timing and area metrics.

Embedded accurate extraction, delay calculation and power calculation engines, integration with signoff tools, Quantus QRC extraction solution, Tempus timing signoff solution, Voltus IC power integrity solution and physical verification system, ensures that there are consistent results across the different steps of the 10nm implementation flow, which improves design closure and signoff schedule predictability.

Global optimisation engines provides optimal performance and power during implementation while taking 10nm process variation into account. Massively parallel architecture increases capacity and drives better turnaround times without compromising the QoR, despite the tight constraints imposed by 10nm technology geometries.