Hitachi adopts Cadence AMS model-based methodology

The results were achieved by comparing the transistor-level and the model-based methodology on the same four CPUs. The significant reduction in the verification cycle time provided Hitachi with the ability to meet time-to-market goals for designs that integrate both analog and digital functions.

With its previous transistor-level methodology, Hitachi predominantly relied on block-level verification followed by tuning analog-digital interfaces to ensure full-chip functionality, which typically required multiple, costly iterations. By using a Verilog-AMS real number modeling and simulation flow supported by a full set of Cadence tools—Virtuoso Analog Design Environment (ADE), Spectre Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Virtuoso AMS Designer and Incisive Enterprise Simulator—Hitachi reduced iterations and met its accuracy requirements, ultimately speeding time to market.