Design

Free Board Analysis

24th September 2010
ES Admin
0
GOEPEL electronics Ltd. offers a free board analysis for Design for Testability (DfT) and opportunities to increase test coverage with Boundary Scan. Application engineers of the Cambridge based Company will provide an analysis of Boundary Scan chain and ICs, project analysis focusing on resolving test issues and optimising test coverage. As a result, there will be recommendations how to increase test coverage, reduce test points and increase the performance of PLD and Flash components.
There are many parts of designs that are not covered by other Boundary Scan Systems but with GOEPEL’s latest advancements in software and hardware more of the design can be tested not just during the manufacturing stage but also the first prototypes where faults are more likely.

Most importantly the analysis can be done once the schematic is complete and before layout starts or in parallel if timescales are tight.

GOEPEL electronics’ service requires the following data:
• Schematic as a searchable PDF
• BSDL files for devices (e.g. ASICs) which are not freely available from the device manufacturer
• Data sheets for special devices
• PCB Netlist (most popular CAD-formats are supported)
• Complete bill of materials (BOM)

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