GOEPEL electronic extends BSDL Testbench to Multi Chip Modules and 3D Chips

“The progressive integration technologies at component level such as 3D chips and Multi-Chip Modules require higher performance of the EDA tools for successful implementation and verification. With our TAPChecker software we smooth the way for such purposes”, says Norbert Muench, Manager EDA Software Team within GOEPEL electronic’s JTAG/Boundary Scan Division. “The fully automatic generation of testbenches guarantees a deeper validation and higher design quality of the target as well as the full functionality of all Boundary Scan structures in practical usage.”
“We have focussed on Boundary Scan as test strategy for our newest multi-die design from the very beginning. That’s why a comprehensive validation of the entire IEEE 1149.1 functions were a must already on the design stage”, explains Daniel Wilkinson, Director of Verification with XMOS Semiconductor. “We discussed this target with the responsible specialists in GOEPEL electronic’s EDA software team. The TAPChecker MCM option was made available as agreed in our design process. We verified our JTAG/Boundary Scan implementation before tape out and then exported patterns from the same tool for our production test program.”
TAPChecker™ is based on a modular platform architecture with central database and individually licensable modules for data import and export as well as automatic test vector generation. The software can be utilised for automatic testbench generation to simulate BSDL files and to provide test vectors for IC testers. It is available for various operating systems such as SOLARIS®, Windows® and LINUX®, supporting IEEE 1149.1 and IEEE 1149.6.