FinFET designs for mobile and HPC platforms
Cadence Design Systems announced several important deliveries in its collaboration with TSMC to advance 7nm FinFET designs for mobile and high-performance computing (HPC) platforms. As a result of the joint work, Cadence digital, signoff and custom/analog tools have achieved certification for the latest Design Rule Manual (DRM) and SPICE for the TSMC 7nm process. In addition, a new process design kit (PDK) enabling customers to achieve optimal power, performance and area (PPA) is now available.
Cadence has also made enhancements to the 7nm Custom Design Reference Flow and library characterisation flow. These design tool advancements have enabled Cadence to accelerate initial deliveries of its high-speed SerDes and low-latency DDR IP cores to leading customers, with test chips expected to tape out in the fourth quarter of this year.
These products represent the first of a comprehensive portfolio of application-optimised 7nm solutions to be developed by Cadence.
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