Making Moves On PCI Standards

PCI Express Generation 2 doubles the transfer speed of Generation 1, from 2.5GHz/lane to 5GHz/lane. The forthcoming Generation 3 will increase this again to 8GHz/lane. An enthusiast for PC/104 is Flemming Christensen, President of Sundance Multiprocessor Technology and Associate Member Director, PC/104 Consortium. He points out that although chipsets do not incorporate Generation 3 yet, the compatibility is assured for when Generation 3 moves into the mainstream in a few years’ time.

The 20 year old PC/104 specification already allows embedded engineers to stack processor boards. With the upgrades to PCI Express, it will be a case of simply plugging in another board without having to redesign the backplane to take advantage of the increased rates. Christensen calls it the ‘option of expanding without the cost of expansion’, as there is no need to allocate slots, as is the case with conventional system boards.

The Consortium wanted a stackable form of PCI Express that was backward-compatible with current specifications for the embedded PC physical and electrical interface standard. It publicised the revision at this year’s Embedded World Conference, Nuremberg. According to Jeff Munch, Chair PCI/104 Consortium, its additions and enhancements exploit the performance improvements afforded by increased speed to be expected with the advent of PCI Express 3.0. The Consortium deemed that the new specification had to support automatic detection of stacking (up or down) and had to have automatic link shifting for universal add-on modules so that embedded developers could make full use of the fast data transfer.

The original PC/104 specification in 1992 defined the 104 form factor as 90.17x95.89mm with a stacking ISA bus. Since then, a PCI bus has been added — the PCI/104-Plus specification, and the PCI-104, which is a PCI bus on the 104 form factor (no ISA bus). The additions of EPIC (Embedded Platform for Industrial Computing) and EPIC Express form factors increased the area size to 115x165mm and the EBX (Embedded Board, eXpandable) is larger again at 146.05x203.20mm to accommodate a computer’s standard I/O and memory.

In this latest revision, PCI/104-Express supports PCI Express and PCI, while PCIe/104 supports only PCI Express. The physical interface retains software compatibility with the existing PCI infrastructure and is designed to be an interchangeable path for the PC architecture across the original 104 and the larger EPIC and EBX form factors while exploiting the growing silicon choices available for PCI Express. It measures 90x96mm.



The provisions for the next PCI Express Generations allow embedded developers to use the fast data transfer of PCI Express 3.0, which increases transfer rates to 2, 8, 16 and 32Gbyte/s in the x1, x4, x8 and x16 links. The original specification’s economic form factor, due to the self-stacking bus (no backplanes or card cages) is preserved. It also retains the rugged construction, with the original connectors and the mounting holes at all four corners to provide resistance to shock and vibration.

Demands Of PCI Express 3.0

Christian Eder, Marketing Manager for congatec, sees the new standard’s increased data throughput as appropriate for next-generation computing needs but its performance does not extend to mobile computing. “PCI 3.0 is not yet in the mobile market, as the price of speed is power consumption,” he says of the trade-off. Instead it is used more in server and local network applications. “For mobile applications, 2.0 is sufficient — at least for the next two years,” he adds.

With the increase in embedded computing projects comes a requirement to differentiate projects. This means increased customisation.

While, generally, a PC/104 off-the-shelf product is adequate for a standard design, for customisation, congatec advocates use of a CoM (Computer on Module). In particular, the use of a Qseven CoM which at 70x70mm is a smaller, open standard than PC/104 (90.17x95.89mm).

The company’s Qseven carrier boards were first introduced in 2008. In that time, the industry has seen many advances. In addition to the doubling of the PCI parallel bus rate, there has also been the growth in the use of the ARM processor. IMS estimates that from 2011 to 2016 the growth of ARM processors in computing motherboards will increase 20% each year. Kontron’s, SMARC Product Marketing Manager, Gerhard Szcuka, thinks this is conservative.

The ARM Factor

Recognising the need for a dedicated ARM CoM standard, the SGET (Standardization Group for Embedded Technologies) has ratified its debut standard, the SMARC (Smart Mobility ARChitecture) for ARM/SoC-based CoMs (Computer on Modules). The standard was showcased at this year’s Embedded World by Kontron, who along with Adlink, was one of the principal architects. It is based on ULP-COM, or ultra-low power computer on modules.

There are three, scalable SMARC CoM families available today. The SMARC-sAMX6i is the revised ULP COM-sAMX61, based on Freescale’s i.MX 6 with single, dual and quad-core ARM Cortex A9 technology. The ULP COM-sA3874i in the new format is the SMARC-sA3874i, using the single core Sitara 3874 microprocessor from Texas Instruments with a 800MHz Cortex A8 core. The graphics model, the SMARC-sAT30 uses the 1.2GHz NVIDIA Tegra 3, quad core Cortex A9 processor and was formerly the ULP COM-sAT30.



The Qseven, scalable module format was introduced in 2008, when the ARM architecture was not so pervasive and was originally for x86 processors alone. Today, however it does support both x86 and ARM devices.

The SMARC specifications will be available for SMARC developers, users and carrier providers to download at the SGET website.

Rather than uniting the embedded community, the introduction of SMARC could deepen divisions. congatec’s Christian Eder maintains that the newcomer’s MXM 3.0 connector occupies more board real estate with its 314 pins, compared to Qseven’s 230 pins using the MXM connector. Szcuka’s reposte is that the newer connector means more pins are available for camera inputs, for example — SMARC has two — targeting notebooks and other mobile devices.

Another reason to introduce the ARM format, says Szcuka, is that young engineers enter the workplace having used ARM at university. “They have grown up with ARM and Linux not Windows,” which will further drive the growth of ARM-based boards. He believes that SMARC will open more markets and release new possibilities for mobile, battery-powered devices that have not yet been addressed.

Although ARM is attractive in mobile applications due to its lower consumption, need for less cooling making housing design easier, the high computing performance of x86 devices mean that ARM is used in industrial handheld or industrial control units rather than consumer applications, says Eder.

As for size, the two formats are vying for the title of smallest form factor. Qseven is 70x70mm and SMARC is 80x50mm. The debate shows no sign of being settled between the two rivals any time soon.

Qseven is primarily for low power applications, incorporating power management and watchdog support for x86 and ARM processors. SMARC is for ARM alone, yet to add to the intrigue for industry watchers, Szcuka does not rule out the introduction of an x86 version at some point.

Although the revision brings PC/104 forward, there is still work to do, according to Christensen. He believes that there is a need for a smaller format option. The use of lane technology means that more can be squeezed into the format, he argues.

It seems that the advent of a new performance level, in the shape of PCI Generation 2 and, further down the line, Generation 3, only brings clamours in the embedded community to push the boundaries further again.