Enterprise emulation platform enables accelerated SoC design

By combining the Palladium Z1 emulation platform with Cadence Xcelium Parallel Logic Simulation, GUC engineers were reportedly able to apply more complex SoC verification test scenarios with full debug visibility, accelerating verification by up to 795 times.

The Palladium Z1 emulation platform allowed GUC to improve system-on-silicon verification and optimise hardware and software integration earlier in the verification process, ensuring high reliability. The compile capabilities included with the Palladium Z1 emulation platform also enabled GUC to achieve more predictable turnaround times for full-chip emulation model builds. This helped GUC engineers to debug quickly and explore design changes 20X faster, which was not feasible with other design methodologies.

In addition to using the Palladium Z1 emulation platform and Xcelium Parallel Logic Simulation, GUC also used other solutions in the Cadence Verification Suite including Verification IP (VIP) and the JasperGold Formal Verification Platform. The broader Cadence Verification Suite provided GUC with automation, debug, tracking, management and measurement of verification tasks across verification flows and engines, which improved productivity and team collaboration. The Palladium Z1 emulation platform enabled congruency with the adjacent verification suite engines, allowing GUC to significantly optimise overall verification productivity, which ultimately led to improved product quality.

Dr Ken Chen, President at Global Unichip Corporation, stated: “A high-performance ASIC verification solution is vital for driving our product innovations and business, and we need to continually strive to improve our overall product quality. After comparing alternative solutions in the market, we selected Cadence’s Palladium Z1 Enterprise Emulation Platform for its effectiveness in ASIC verification productivity and use-model versatility.

“Adopting the Palladium Z1 emulation platform in conjunction with Xcelium Parallel Logic Simulation and the broader Cadence Verification Suite has enabled us to deliver flexible ASIC services that elevate our visionary IC customers to the next level of leadership in their respective markets.”

The Palladium Z1 Enterprise Emulation Platform is part of the Cadence Verification Suite. It supports the company’s System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of JasperGold, Xcelium, Palladium Z1 and Protium S1 core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.