Emulation technology accelerates software bring-up time

The adapter expands the customer’s use model and enables teams to extract the most value out of their hardware investment. It allows engineers to interface virtually with peripherals, providing the flexibility to run jobs without physical constraints, and improving debug efficiency by augmenting physical debug with virtual debug capabilities for repeatable debug and controlled error injection. Through a balanced distribution of verification tasks between in-circuit and virtual emulation and smooth integration with other Cadence tools such as Palladium Hybrid, design teams can maximise their hardware investments and reduce overall software bring-up time.

“Virtual emulation is a key capability for software-driven hardware verification and system validation,” said Dr. Anirudh Devgan, Executive Vice President and General Manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Coupled with our Palladium Z1 emulator, the VirtualBridge Adapter enables our users to further shorten their development cycle as they are pressed to bring quality products to market quickly.”

The VirtualBridge Adapter further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

“Cadence’s VirtualBridge Adapter enables us to implement complex, multi-GPU configurations with ease,” said Narendra Konda, Director of hardware engineering at NVIDIA. “It complements the Palladium Z1 platform’s in-circuit emulation testing capability and enables us to run our applications and drivers earlier in our development cycle.”