Design tools certified for 3D chip stacking technology

24th April 2019

Mick Elliott

0 0

TSMC has certified Cadence Design System’s design solutions for the new TSMC System-on-Integrated-Chips (TSMC-SoIC) 3D advanced chip stacking technology, which integrates heterogenous chips—including logic ICs and memory—that are fabricated on different process nodes onto a single chip stack for a subsequent packaging process.

A full suite of Cadence digital and signoff, custom/analogue, and IC package and PCB analysis tools have been optimised for TSMC’s SoIC chip stacking technology, enabling mutual customers that require heterogenous chipset integration capabilities to create complex designs more efficiently.

SoIC, TSMC’s multi-chip stacking techniques, expands upon TSMC’s 3D Wafer-on-Wafer (WoW) and Chip-on-Wafer (CoW) technologies and address the diverse design requirements for emerging applications, including 5G, AI, IoT and automotive applications.

TSMC and Cadence collaborated to enhance tools, methodologies and flows, supporting mutual customers to manage the overall connectivity and verification of their chip integration solutions as part of the overall design. The entire design cycle is enabled with multiple 3D featured tools working together.

The Cadence tools in the flow include the Innovus Implementation System, Quantus Extraction Solution, Voltus IC Power Integrity Solution, Tempus Timing Signoff Solution, Physical Verification System (PVS), Virtuoso custom IC design platform, SiP Layout, OrbitIO interconnect designer, Sigrity PowerSI3D EM Extraction Option, Sigrity PowerDC technology, Sigrity XcitePI Extraction, Sigrity XtractIM technology and Sigrity SystemSI technology.