DDR4 SDRAM IP design and verification solution available

Northwest Logic provides silicon-proven, high-performance, easy-to-use memory controller design IP for use in both ASICs and FPGAs along with a comprehensive set of add-on cores, while Krivi Semiconductor offers state-of-the-art DDR PHY with DFI compatibility and minimum integration overhead. Mentor Graphics supplies a comprehensive, configurable, ready-to-go verification IP tool suite for memory controllers and interfaces.

The Mentor Graphics IP Partnership Program provides a complete ecosystem enabling rapid integration of design and verification IP for ASIC and FPGA design teams. By enabling early access to design IP from leading suppliers by Mentor Graphics, and reciprocal early access to Mentor Graphics’ Questa Verification IP (QVIP) by leading design IP suppliers, the program provides high performance, high quality, pre-validated design IP, and pre-configured, easy-to-use, ready-to-go verification IP. As a result, SoC project teams can cut their IP design and verification time in half.

“The partnership between independent design IP and verification IP suppliers ensures unbiased validation,” said Mark Olen, Mentor Graphics product marketing group manager. “Working with Northwest Logic and Krivi Semiconductor enables our mutual ASIC and FPGA customers to integrate their DDR4 SDRAM design IP in half the time, while providing the highest levels of impartial verification quality.”

Northwest Logic provides its high-performance, high-quality, easy-to-use “To the Point Solutions” through a combination of design IP and services. “Our DDR4 SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability,” said Brian Daellenbach, President of Northwest Logic. “By working with Krivi Semiconductor and Mentor Graphics, our customers have access to a complete DDR4 PHY, controller, and advanced verification solution.”

Krivi Semiconductor offers state-of-the-art DDR PHY with DFI compatibility and minimum integration overhead. “We have exhaustively validated our Multi-DDR PHY solution using Mentor Graphics DDR Questa VIP,” said Gyan Prakash, CTO. “We are pleased to work with memory controller vendors such as Northwest Logic, and become part of Mentor’s IP/VIP ecosystem.”

Mentor Graphics’ QVIP library provides engineers with standard UVM SystemVerilog components using a common architecture across a wide range of protocols, including DDR4 SDRAM memory. Test plans, compliance tests, test sequences, and protocol coverage are all included in source code format, allowing easy re-use, customisation, and debug. The QVIP components also include a comprehensive set of protocol checks, error injection, and debug capabilities.