CST introduces significant new features for EDA simulation

In order to be most effective in the EDA workflow, simulation should be fast and accurate and offer a more detailed understanding of the causes of signal and power integrity and EMC issues than measurement alone can provide. For this reason, CST is introducing several new features in CST STUDIO SUITE 2015 which have been developed to accelerate the simulation process and make it easier for users to analyse and optimise their designs.

Before any simulation can begin, a mesh needs to be created to discretise the structure. CST STUDIO SUITE 2015 introduces a tetrahedral meshing algorithm which is optimised for printed electronics. This algorithm exploits knowledge of the general structure of imported models such as PCBs and packages to assemble and mesh them much faster. For frequency domain simulations of complex packages, this can reduce the total meshing time sevenfold.

Another significant new feature is the introduction of Pareto frontier optimisation for decoupling capacitors. The placement of decoupling capacitors can significantly improve the power integrity performance of a PCB, but also increases the cost of fabrication. With Pareto frontier optimisation, the software can automatically balance the two competing design goals and find the combination of capacitors that minimises the cost while meeting the design requirements.

Alongside these major improvements, CST STUDIO SUITE 2015 also includes a range of other performance and productivity improvements developed to make the integration of simulation into the EDA workflow easier and more powerful.

More information about CST’s EDA offering can be found at electronica 2014 at the CST booth, A1.262.