JTAG CoreCommander checks-out FPGA Zone

Forming part of its exciting range of ETP (Embedded Test and Programming) products, CoreCommander FPGA is aimed primarily at hardware design and test engineers.

The base of CoreCommander for FPGAs uses a translator block to access proprietary IP cores through commonly implemented bus structures such as ‘Wishbone’, AMBA, Avalon and CoreConnect. This translator block, provided as a VHDL module, can be either permanently or temporarily programmed into a gate–array. Linker software provided with the module automatically links the translator block with IP blocks to build the complete (test) design to be programmed in the FPGA.

Use of CoreCommander functions can be either interactive or ‘automatic’ - via library routines in a scripting environment. The interactive mode is intended for use by design engineers to interrogate and control the IP blocks in their FPGA during debug. The automatic mode however is more likely to find favour during (at-speed) logic cluster testing in manufacturing.

Together with interconnect testing, logic device ‘cluster’ testing has been one of the mainstays of JTAG/boundary-scan board testing since its inception over 20 years ago. However, in recent years the capacity of the simple (low-speed) boundary-scan register (BSR) to cope with sophisticated command and control requirements of parts like DDR memory has diminished to the point that tests can be compromised. By harnessing the ‘horsepower’ built into devices like microprocessors and now FPGAs, JTAG testing is again re-energised allowing the connections to timing sensitive devices to once again be fully tested and at functional speeds.

MD for JTAG Technologies, Peter van den Eijnden, states: ‘We wanted to implement faster testing of peripherals using our standard JTAG hardware and software tools but without reinventing the wheels for peripheral interface blocks. Since CoreCommander FPGA can link with so much standard IP, it massively simplifies the operation and at the same time brings the cost to a much more attainable level when compared to other FPGA-powered concepts.”