Cadence, STMicro partner for VSR SerDes 7nm tape out

Cadence provided the critical IP architecture, certain IP sub-blocks and relevant design support, leveraging its investments in 56G and 112G PAM4 SerDes technology while ST developed the complete SerDes core, making use of its extensive know-how in this field.

“Cadence’s strong 112G SerDes fully hits the requirements relevant to ASICs for networking and communication,” said Flavio Benetti, general manager of the ASIC division at STMicroelectronics. “By combining Cadence’s silicon-proven IP building blocks with our deep knowledge of SerDes analogue and mixed-signal design techniques, we were able to beat our customer’s challenging power targets. We value our ongoing collaboration and have selected Cadence as our preferred supplier for 112G long-reach SerDes IP.”

“Our successful collaboration with STMicroelectronics exemplifies how Cadence is delivering SoC design excellence through our Intelligent System Design strategy,” said Babu Mandava (pictured), senior vice president and general manager of the IP group at Cadence. “Our silicon-proven PAM4 SerDes IP portfolio optimised for power, performance and area efficiency, used in conjunction with the Cadence Innovus Implementation System, enabled ST to achieve performance excellence and time-to-market advantage for their innovative designs.”

The broad Cadence design IP portfolio including the 112G Multi-Rate PAM4 SerDes, and the best-in-class digital and signoff technology including the Innovus Implementation System, both support Cadence’s Intelligent System Design strategy, enabling customers to achieve SoC design excellence.