Cadence Palladium XP Enables QLogic to Rapidly Develop Sophisticated Network Switch

Using the Palladium XP system, QLogic dramatically reduced the design time associated with developing a complex, multi-million-gate system-on-chip (SoC) needed to drive scalable, non-blocking switch architectures across the various protocols required from datacenter-class switching solutions.



“QLogic continues to expand its market share by delivering technologies that transform data centers and storage networks around the globe,” said Jesse Parker, vice president and general manager, Network Solutions Group, QLogic. “Specialized SoCs are a critical element that enable us to deliver network switches optimized for the power, performance and bandwidth requirements of our customers. The Palladium XP platform gave us the ability to test our design at the system level much earlier in the design cycle and much faster than ever before.”



“At the forefront of high performance network switch design, QLogic is a prime example of how customers rely on Palladium XP to ensure they can deliver industry-leading system solutions in tight time-to-market constraints,” said Michał Siwiński, group director of product marketing, System & Software Realization Group at Cadence. “By delivering a critical platform that enables on-time SoC and system development, Cadence is helping the world’s leading semiconductor and systems companies maintain their competitive edge.”



Palladium XP Verification Computing Platform, part of the Cadence System Development Suite, unifies simulation, acceleration and emulation capabilities in a single environment, enabling efficient hardware-software system verification.



The platform enabled QLogic to explore the complex interaction of buses, ports and crossbars simultaneously at the system level. QLogic leveraged the capacity, speed and debugging capabilities of the Palladium XP to reduce the verification time associated with its latest design, even as compared to earlier, less complex switches. Featuring a much deeper trace buffer, Palladium XP gave QLogic the ability to examine a trace window that was more than 10x the size of previous-generation switches – a requirement for system-level verification of high-node-count switch designs.



Palladium XP also provided the capacity required for the creation of a synthesizable test bench. QLogic was able to incorporate test-bench parameters into read-only memory (ROM) for advanced system-level testing. The highly scalable system easily accommodated the QLogic multimillion-gate design, while giving the company room to grow for next-generation designs.