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Cadence Incisive Enterprise Simulator Improves Low-Power Verification Productivity By 30%

7th May 2013

ES Admin

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Cadence Design Systems today introduced a new version of Incisive Enterprise Simulator, with features that improve low-power verification productivity of complex SoCs by thirty percent. The 13.1 release of Cadence Incisive Enterprise Simulator addresses low-power verification challenges for advanced modeling, debug, power format support and to provide faster verification for today’s most complex SoCs.

The new debug features in Incisive SimVision Debugger provide simple visualization and interactive debug of both complex text-based power intent standards. Other simulator enhancements include additional SystemVerilog support and faster elaboration to turn around simulation jobs much more quickly. Enhanced support for CPF and newly added support of IEEE 1801 will make these enhancements available to all low-power engineers.

“We successfully ran the Unified Power Format (IEEE 1801 / UPF) simulation with the Incisive Enterprise Simulator to identify power domains, verify isolation, and more,” said David Vincenzoni, R&D design manager at STMicroelectronics. “The tool works well and we applaud Cadence for adding the new advanced verification capabilities and IEEE 1801 support that will help speed the completion of our low-power SoCs.”

“As power demands grow with chip complexity, new low-power verification capabilities are required to adequately validate designs before they head to implementation,” said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “The latest release of Incisive Enterprise Simulator features new capabilities that ease the challenge of verifying all of today’s power-aware designs.”