Cadence Encounter and Virtuoso Design Platforms Receive TSMC 20nm Phase I Certification

Early adopters are using the flows and tools while close collaboration continues between TSMC, Cadence and designers.

The Cadence Encounter RTL-to-GDSII digital flow includes support for 20-nanometer rules, and innovative patterning placement, optimization, clocking, and routing. For custom/analog, certification covers advanced Virtuoso SKILL Pcell abutment to address complex device-level rules, and in-design loop detection using signoff quality DRC with the integrated Cadence Physical Verification System.

In signoff, Cadence QRC Extraction and Cadence PVS, including full DRC/LVS physical verification, and Encounter Power System for electromigration and IR have been certified. The companies are working toward certification for Encounter Timing System.

“Close collaboration with TSMC and joint R&D efforts have led to this important milestone,” said Dave Desharnais, group director of product marketing, Silicon Realization Group. “We are working closely with the world’s leading semiconductor companies, and this certification helps pave the way for them to reap the benefits of a smooth transition to the 20-nanometer node.”

“TSMC certification is an important milestone for 20-nanometer readiness,” said Suk Lee, senior director of Design Infrastructure Marketing at TSMC. “Our ongoing work with Cadence demonstrates how collaboration accelerates innovation and benefits the advanced design community.”