Cadence enables a 60% reduction in packaging design time

OrbitIO and SiP Layout enable automated IC/package/PCB interconnect design and optimisation. This capability can better optimise the interconnect pathways for routing and signal/power integrity performance as compared to the current methods of using static spreadsheets. The multi-substrate interconnect pathway design optimises design performance and minimises substrate complexity and cost by allowing tradeoff exploration and decisions early in the process. By implementing this process, Cadence is able to reduce the typical spreadsheet-based bump/ball map planning studies from days/weeks with multiple iterations to just a few hours with little to no iterations using the single multi-fabric environment of the OrbitIO interconnect designer.

Jim Wang, Senior Associate Vice President, Faraday, commented: “Die bump planning and optimisation is a critical part of our SoC and ASIC design process in order to meet our performance goals. Using OrbitIO helps us achieve our goals in an efficient manner and enabled us to reduce design time by up to 60%, while delivering the quality of results our customers expect.”

“With our customers’ needs as top priority, we enhanced the OrbitIO Interconnect Designer, which contributed to a fully automated methodology for optimising cross-domain interconnect pathways. The result is a streamlined design flow that leads to reduced design cycles and lower product development costs," added Saugat Sen, Vice President, R&D, PCB and IC Packaging Group, Cadence.