Cadence design tools get thumbs-up from TSMC

Cadence and TSMC are working with customers on N6 design starts both on production designs and test chips. Additionally, Cadence and TSMC have active N5/N5P customer engagements underway.

The certified tools support the Cadence Intelligent System Design strategy, enabling customers to achieve SoC design excellence. Cadence’s integrated flow ensures that all the tools will work together seamlessly, and customers can download the corresponding N6 and N5/N5P process design kits (PDKs) to begin design projects now.

Cadence delivered a fully integrated digital implementation and signoff tool flow, which has been certified on both TSMC’s N6 and N5/N5P process technologies.

The Cadence full flow includes the Innovus Implementation System, Liberate Characterisation, Liberate Variety Statistical Characterisation, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution and Pegasus Verification System.

Additionally, the Genus Synthesis Solution is enabled for these process technologies.

The Cadence digital and signoff tools provide EUV support across the flow, offering customers optimal power, performance and area (PPA).

Some of the latest Cadence tool enhancements include expanded EUV layer support and back end of line (BEOL) layer modeling and middle end of line (MEOL) features.

The Cadence custom/analogue tools certified on TSMC’s N6 and N5/N5P process technologies include the Spectre Accelerated Parallel Simulator (APS), Spectre X, Spectre eXtensive Partitioning Simulator (XPS), Spectre RF Option, Spectre Circuit Simulator, and Voltus-Fi Custom Power Integrity Solution, as well as the Virtuoso custom IC design platform, which consists of the Virtuoso Schematic Editor, Virtuoso Layout Suite and Virtuoso ADE Product Suite.