Cadence Boosts Verification Productivity for Complex FPGA/ASIC Design

The capabilities announced today target inefficiencies that exist in verification flows for many of today’s advanced node designs. As design complexity has grown, verification flows have often become fractured and inefficient, with separate niche flows created to address such challenges as mixed-signal, low-power and formal analysis. The new capabilities bind these niches through MDV and novel technology that supports the unique end-to-end Cadence® approach to Silicon Realization—a key tenet of the EDA360 vision that focuses on unified intent, abstraction and convergence.

With the new release of the Cadence Incisive® technology, verification engineers can merge coverage data from formal analysis and simulation engines within a unified verification plan. Additional abilities that expand the scope of the verification intent include support for enhanced low-power corruption and isolation simulation as well as automation for combining and mixing simulation and formal technologies.

As the leading supplier of automated test equipment, verification is key to our business, said Rick Burns, senior director of hardware engineering at Teradyne, Inc. Three years ago, we added MDV to improve the predictability and quality of our FPGA and ASIC development projects. The new Silicon Realization capabilities of Cadence's Incisive digital verification and Virtuoso® analog simulation will lead to further improvement. As a result, our customers can have continued confidence in our development schedules, which will help us close more business.

With this latest technology, earlier bug detection is enabled through additional abstraction capability, including support of the forthcoming UVM 1.0 standard for testbench verification. Leveraging 10 years of experience with methodology leading to the UVM, Cadence is delivering additional methodology support and metrics collection based on the UVM, including low-power, mixed-signal, and acceleration methodologies. Features such as validation of digital mixed-signal models against detailed transistor models, debug support for macros and finite state machines, and reference implementations of these methodologies in the Incisive Verification Kit enable project teams to improve their productivity.

In addition, improving engine performance enables faster convergence of the verification process to the verification plan. For customers running thousands of regression tests, the new Incisive Specman Advanced Option provides reseeding and dynamic loading of e-based tests, multi-core e code compilation, and the ability to shorten debug mixing interpreted and compiled code improving overall productivity by greater than 1.4 times. Other capabilities to speed convergence include support for multi-core formal analysis and 1.3-times faster SystemVerilog testbench simulations.

Engine-level performance alone is simply not enough to solve the verification problem, said Thomas Anderson, product management group director at Cadence. Verification has fractured into niches during the past decade as complexity increased and teams needed to focus. This prevented a unified verification flow, making it very difficult to predict the verification process or know where in that process any particular project was. Our metric-driven approach, with the help of these new enhancements, changes all that with a unified verification plan, flow and metrics.