Cadence Accelerates Development of Multiprocessor Mobile Devices with New ARM ACE Verification IP

The new VIP enables designers to verify the functionality of multiprocessor ARM Cortex®-A15 designs now being deployed in a variety of mobile applications including consumer tablets and smart phones. These multiprocessor designs must rely on cache coherency to effectively execute multiple tasks simultaneously, a requirement in order to run more powerful software “apps” with fast response times. The ACE protocol provides hardware-based cache coherency and is used in conjunction with ARM Cortex-A15-based multiprocessor designs. When using the ACE VIP in tandem with Cadence® end-to-end interconnect fabric monitoring, designers have the first full solution for coherency verification.



“Mobile design complexity has grown to the point that it requires capabilities previously only found in very high-performance systems,” said Michael Dimelow, Director of Marketing, Processor Division, ARM. “The ACE protocol provides the cache coherency required to manage the rising number of transactions between multiple processors and distributed memory. This is true for all classes of consumer devices and, increasingly, in the network and enterprise markets. ARM has worked closely with EDA partners, such as Cadence, to ensure that their latest VIP tools are capable of validating these complex coherent compute systems.”



The AMBA 4 ACE VIP is the newest member of the Cadence VIP catalog, which is comprised of a broad portfolio of protocol verification IP and memory models. VIP enables designers to verify the functionality of their systems at the silicon, SoC and system levels, delivering the technology required to achieve the Cadence EDA360 vision.



“By working collaboratively with ARM and their leading Cortex-A15 customers over the last year, we deliver must-have VIP for verifying systems based on the ACE protocol,” said Ziv Binyamini, Corporate Vice President of System & Software Solutions, Research and Development at Cadence. “This VIP is critically needed to speed the development and delivery of sophisticated ARM-based mobile devices and overcome the growing challenges inherent in designing cache-coherent, multiprocessor systems.”



For over ten years, on more than 1600 designs, the advanced methodology used by Cadence VIP has helped to measurably verify that AMBA designs will meet the specification. Now, with the complex use scenarios introduced with cache coherency and multiprocessor designs, Cadence’s advanced VIP is even more critical to complete design verification. Cadence VIP verifies each master and slave to ensure compliance with the ACE specification, and works with an interconnect fabric monitor to ensure coherency of the full SoC, giving designers confidence that their designs are truly coherent. Only Cadence delivers this complete ACE verification solution.