austriamicrosystems releases new version of best-in-class process design kit for its 0.18µm High-Voltage CMOS technology

Based on Cadence Virtuoso custom design platform (IC 5.1.41 release), the new HIT-Kit significantly improves the time-to-market for highly competitive products in the analog intensive mixed signal and System-on-Chip arena. Supporting designers in creating their first-time-right mixed signal designs even for complex designs, this comprehensive design kit with its highly accurate simulation models and flexible pcells provides a proven route to silicon.

The new HIT-Kit v3.77 supports the 0.18µm specialty process technology H18 (High-Voltage CMOS) which is based on IBM’s industry proven foundry process technology CMOS7RF. It includes silicon-qualified digital, analog and RF library elements, complete sets of low voltage devices (1.8V and 5.0V) and high-voltage devices with various gate oxide thicknesses (20V and 50V devices). Fully characterized simulation models for a large set of simulators, extraction and verification run sets as well as automatic layout device generators complete the H18 HIT-Kit offering. Hence product developers are enabled with a plug-and-play tool set which facilitates first time right designs.

The H18 process is already the 6th generation of High-Voltage CMOS processes developed at austriamicrosystems and it is now ready for design and risk production. This new HIT-Kit v3.77 is a result of austriamicrosystems continuous efforts to deliver best-in-class design environment and analog foundry services to our customers, states Thomas Riener, Vice President and General Manager Full Service Foundry at austriamicrosystems. The usage of the new HIT-Kit enables our customers to access our new 0.18µm High-Voltage CMOS specialty process.

The digital standard cell libraries included in this H18 HIT-Kit have a gate density of 118kGates/mm² and are available both in standard and low leakage versions. Furthermore all I/O structures within the design kit are silicon-validated and meet the military ESD and JEDEC latch-up standards with I/O pads designed to surpass 4kV HBM and 250mA latch-up immunity.